Simulation Results: rom_ctrl/64kb

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.92 %
  • code
  • 99.20 %
  • assert
  • 96.80 %
  • func
  • 94.75 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 99.67 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.880s 632.375us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.260s 223.639us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.930s 515.016us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.440s 294.157us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.050s 1871.016us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.660s 409.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.930s 515.016us 1 1 100.00
rom_ctrl_csr_aliasing 6.050s 1871.016us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.760s 1065.109us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.320s 649.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.380s 300.371us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.280s 3191.875us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.090s 1427.706us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.340s 544.207us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.570s 577.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.570s 577.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.260s 223.639us 1 1 100.00
rom_ctrl_csr_rw 6.930s 515.016us 1 1 100.00
rom_ctrl_csr_aliasing 6.050s 1871.016us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.810s 305.137us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.260s 223.639us 1 1 100.00
rom_ctrl_csr_rw 6.930s 515.016us 1 1 100.00
rom_ctrl_csr_aliasing 6.050s 1871.016us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.810s 305.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.430s 754.948us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
rom_ctrl_tl_intg_err 49.960s 963.941us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.880s 632.375us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.880s 632.375us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.880s 632.375us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.960s 963.941us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
rom_ctrl_kmac_err_chk 12.090s 1427.706us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 146.810s 9601.064us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.430s 754.948us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 230.370s 2361.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 18.190s 2568.561us 1 1 100.00