Simulation Results: rstmgr

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.17 %
  • code
  • 99.21 %
  • assert
  • 97.44 %
  • func
  • 91.87 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.340s 66.619us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.020s 65.036us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 1.970s 50.998us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.180s 44.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.100s 66.418us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00
rstmgr_csr_aliasing 1.180s 44.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.040s 104.178us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.070s 41.302us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 50.217us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.510s 609.248us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.510s 609.248us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.510s 609.248us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.510s 609.248us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 11.040s 1671.301us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.040s 36.755us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.430s 40.598us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.430s 40.598us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 65.036us 1 1 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00
rstmgr_csr_aliasing 1.180s 44.359us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 40.451us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.020s 65.036us 1 1 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00
rstmgr_csr_aliasing 1.180s 44.359us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 40.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.830s 3391.766us 1 1 100.00
rstmgr_tl_intg_err 2.300s 331.552us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.830s 3391.766us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.830s 3391.766us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.300s 331.552us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.050s 61.779us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.990s 459.133us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.250s 291.858us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.830s 3391.766us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 37.340us 1 1 100.00