Simulation Results

Simulation Results: rv_dm/use_dmi_interface

29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.85 %

code
73.69 %

assert
96.16 %

func
48.70 %

line
90.58 %

branch
74.79 %

cond
76.32 %

toggle
70.52 %

FSM
56.25 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	6.520s	6457.676us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	0.850s	171.322us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.700s	1085.495us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	34.460s	39843.167us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.350s	335.071us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	1.740s	4140.851us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	13.370s	6344.609us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	114.560s	63849.558us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	71.490s	138553.302us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	0.930s	166.518us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.220s	344.760us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.130s	401.996us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.920s	473.824us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.020s	188.584us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	0.830s	396.525us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.730s	128.165us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.110s	651.490us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	0.930s	166.518us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.980s	243.492us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	0.970s	392.490us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.130s	401.996us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.820s	101.306us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	2.880s	530.852us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.720s	79.701us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	51.710s	40710.415us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	23.190s	2401.598us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	2.720s	1013.531us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	23.190s	2401.598us	1	1	100.00
	rv_dm_csr_rw	1.720s	79.701us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.740s	132.832us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.770s	77.035us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	6.520s	6457.676us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.390s	792.682us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.760s	153.530us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.730s	329.470us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.670s	531.064us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	2.150s	2077.996us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	0.960s	335.073us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	0.700s	80.359us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	0.840s	125.153us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.810s	166.762us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	3.240s	1179.923us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.630s	727.093us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.740s	52.571us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	3.930s	12383.867us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	58.260s	3642.864us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.770s	98.093us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	1.690s	1040.473us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.840s	78.502us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.350s	183.745us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.350s	183.745us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	23.190s	2401.598us	1	1	100.00
	rv_dm_csr_hw_reset	2.880s	530.852us	1	1	100.00
	rv_dm_csr_rw	1.720s	79.701us	1	1	100.00
	rv_dm_same_csr_outstanding	3.030s	214.002us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	23.190s	2401.598us	1	1	100.00
	rv_dm_csr_hw_reset	2.880s	530.852us	1	1	100.00
	rv_dm_csr_rw	1.720s	79.701us	1	1	100.00
	rv_dm_same_csr_outstanding	3.030s	214.002us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	2.030s	2145.979us	1	1	100.00
	rv_dm_tl_intg_err	10.090s	2026.187us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	10.090s	2026.187us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.240s	1179.923us	1	1	100.00
	rv_dm_debug_disabled	1.020s	125.416us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	3.240s	1179.923us	1	1	100.00
	rv_dm_debug_disabled	1.020s	125.416us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	6.520s	6457.676us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	0.880s	119.180us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.750s	106.018us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.750s	106.018us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	0.880s	119.180us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	4.460s	271.058us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	280.920s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:
	rv_dm_sba_tl_access	106687151326201309851176277834108403478265161394376664537170153476574240468525	86	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @5399
Error-[CNST-CIF] Constraints inconsistency failure
	rv_dm_delayed_resp_sba_tl_access	7400292636592570496043542723372503559289811227295944479327809983233130796264	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
	rv_dm_bad_sba_tl_access	84524123463900183750166665117531358254125304891802137774202168074882219742716	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
	rv_dm_autoincr_sba_tl_access	114037056644469912688891065128314076341414722138335744020069956291858090007890	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	4484214745899893435078103892779288444997816833090127873183837013454866931003	77	UVM_INFO @ 473823786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	102439078706520812898473357286659615717277995345822157734942257946786147661486	77	UVM_INFO @ 52571291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	26341337473814245361020575658716584006747105030320891742197010180645452055394	77	UVM_INFO @ 166762401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	82310270303094193532386563037888406444319297563684848811334808190388871774693	80	UVM_INFO @ 1040472900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_scanmode	88947268393138330353536378272364175434458161567298141989928760784457089029654	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
	rv_dm_stress_all_with_rand_reset	53860409068498817383053371512993002836131675269486911700618089242020635405776	89	UVM_INFO @ 271057881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---