Simulation Results: rv_timer

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.82 %
  • code
  • 100.00 %
  • assert
  • 95.22 %
  • func
  • 98.24 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.020s 1176.222us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 12.607us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.540s 38.321us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.170s 1325.590us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 87.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.020s 64.441us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.540s 38.321us 1 1 100.00
rv_timer_csr_aliasing 0.770s 87.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.380s 919.093us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.300s 2001.764us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 149.760s 373891.415us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 149.760s 373891.415us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 8.060s 4774.468us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.590s 29.839us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 39.809us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.070s 22.766us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.070s 22.766us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 12.607us 1 1 100.00
rv_timer_csr_rw 0.540s 38.321us 1 1 100.00
rv_timer_csr_aliasing 0.770s 87.612us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 18.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 12.607us 1 1 100.00
rv_timer_csr_rw 0.540s 38.321us 1 1 100.00
rv_timer_csr_aliasing 0.770s 87.612us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 18.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.900s 431.455us 1 1 100.00
rv_timer_tl_intg_err 1.180s 443.738us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.180s 443.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.590s 43.523us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.700s 90.399us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 43.850s 18139.274us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 57375399155909849421613381900006878145458025632108665727912282338206148551467 76
UVM_INFO @ 90399084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 50470955009650669377974819857938970206330771194683726273263301160727797783703 77
UVM_INFO @ 919092673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---