Simulation Results: spi_device/1r1w

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 93.15 %
  • assert
  • 94.64 %
  • func
  • 71.03 %
  • line
  • 99.04 %
  • branch
  • 98.25 %
  • cond
  • 95.56 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 180.450s 113101.687us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.230s 284.259us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.320s 43.217us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.450s 13023.461us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.130s 2500.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.780s 148.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.320s 43.217us 1 1 100.00
spi_device_csr_aliasing 11.130s 2500.243us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.650s 12.689us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.620s 248.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 33.182us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.830s 2.577us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.740s 3.698us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.720s 65.459us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.720s 65.459us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.860s 34.762us 1 1 100.00
spi_device_tpm_sts_read 0.980s 52.003us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 12.490s 17800.589us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 16.360s 33075.050us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.180s 1723.912us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.180s 1723.912us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.440s 841.894us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.440s 841.894us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.440s 841.894us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.440s 841.894us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.440s 841.894us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.300s 1026.255us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.480s 1626.422us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.480s 1626.422us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.480s 1626.422us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.920s 8373.099us 1 1 100.00
spi_device_read_buffer_direct 3.600s 1308.299us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.480s 1626.422us 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 19.390s 6299.349us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.020s 135.936us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.020s 135.936us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 180.450s 113101.687us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 327.220s 57015.548us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 50.850s 5033.863us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 81.051us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.860s 11.911us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.120s 63.474us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.120s 63.474us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.230s 284.259us 1 1 100.00
spi_device_csr_rw 1.320s 43.217us 1 1 100.00
spi_device_csr_aliasing 11.130s 2500.243us 1 1 100.00
spi_device_same_csr_outstanding 1.700s 322.937us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.230s 284.259us 1 1 100.00
spi_device_csr_rw 1.320s 43.217us 1 1 100.00
spi_device_csr_aliasing 11.130s 2500.243us 1 1 100.00
spi_device_same_csr_outstanding 1.700s 322.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.320s 90.377us 1 1 100.00
spi_device_tl_intg_err 5.670s 429.157us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.670s 429.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 18.370s 3169.677us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 52472387143869797389825235188921122279276634555820401902650445146191917851105 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2210086 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2210086 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[948])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 52142500199115368430065954747966523826181159091408767282876115214325443449807 76
UVM_ERROR @ 1162624 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2c671 [110000101100011001110001] vs 0x0 [0])
UVM_ERROR @ 1188624 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb56be1 [101101010110101111100001] vs 0x0 [0])
UVM_ERROR @ 1218624 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x348ca5 [1101001000110010100101] vs 0x0 [0])
UVM_ERROR @ 1266624 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe81b20 [111010000001101100100000] vs 0x0 [0])