Simulation Results: spi_host

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 94.93 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.91 %
  • line
  • 98.65 %
  • branch
  • 93.25 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 20.000s 1758.113us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 49.673us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 22.627us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 92.517us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 41.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 38.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 22.627us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.408us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.844us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 22.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.560us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 81.104us 1 1 100.00
spi_host_error_cmd 1.000s 21.027us 1 1 100.00
spi_host_event 4.000s 383.309us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 96.583us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 96.583us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 96.583us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 236.099us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 34.827us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 96.583us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 96.583us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 20.000s 1758.113us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 20.000s 1758.113us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 71.000s 2425.342us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 624.062us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 93.000s 6387.443us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 108.502us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 81.104us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 51.140us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 28.206us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 120.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 120.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 49.673us 1 1 100.00
spi_host_csr_rw 1.000s 22.627us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.408us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 26.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 49.673us 1 1 100.00
spi_host_csr_rw 1.000s 22.627us 1 1 100.00
spi_host_csr_aliasing 1.000s 41.408us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 26.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 99.355us 1 1 100.00
spi_host_sec_cm 1.000s 43.319us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 99.355us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 105.000s 9507.467us 1 1 100.00