Simulation Results: sram_ctrl/main

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.13 %
  • code
  • 95.42 %
  • assert
  • 96.19 %
  • func
  • 93.80 %
  • block
  • 94.26 %
  • line
  • 94.81 %
  • branch
  • 90.76 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 738.367us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.437us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.286us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 337.230us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 99.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 627.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.286us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 99.413us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 90.000s 10950.475us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 92.000s 24604.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 32.000s 14053.769us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 199.000s 4991.779us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 144.000s 14708.713us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 46.000s 9954.873us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 21.000s 6316.213us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1401.567us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 387.300us 1 1 100.00
sram_ctrl_partial_access_b2b 262.000s 47848.227us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 3925.664us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2660.258us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 1405.051us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2836.225us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1359.348us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 94.000s 98059.357us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 31.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 252.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 252.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.437us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.286us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 99.413us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.850us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.437us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.286us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 99.413us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3803.322us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 373.283us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 373.283us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2836.225us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 2836.225us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.286us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1401.567us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1401.567us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1401.567us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 21.000s 6316.213us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 686.699us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3803.322us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 1389.501us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 738.367us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 738.367us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1401.567us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 21.000s 6316.213us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 738.367us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 376.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 520.928us 1 1 100.00