Simulation Results: uart

 
29/04/2026 19:39:04 DVSim: v1.33.0 sha: a64a82b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.62 %
  • code
  • 96.74 %
  • assert
  • 97.12 %
  • func
  • 44.99 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.960s 291.813us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 38.536us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 47.613us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.430s 132.145us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 207.386us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.060s 70.669us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 47.613us 1 1 100.00
uart_csr_aliasing 0.820s 207.386us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 27.410s 22875.794us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.960s 291.813us 1 1 100.00
uart_tx_rx 27.410s 22875.794us 1 1 100.00
parity_error 2 2 100.00
uart_intr 22.910s 18272.402us 1 1 100.00
uart_rx_parity_err 13.280s 9170.513us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 27.410s 22875.794us 1 1 100.00
uart_intr 22.910s 18272.402us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 17.600s 14003.206us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 26.690s 18871.043us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 100.600s 83584.586us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 22.910s 18272.402us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 22.910s 18272.402us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 22.910s 18272.402us 1 1 100.00
perf 1 1 100.00
uart_perf 108.460s 18883.489us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.420s 10728.550us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.420s 10728.550us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 43.620s 27801.034us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 56.420s 47158.645us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.110s 1061.544us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 43.100s 6762.503us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 89.730s 286956.742us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 27.270s 72011.526us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.540s 93.814us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 68.103us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.350s 44.189us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.350s 44.189us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 38.536us 1 1 100.00
uart_csr_rw 0.630s 47.613us 1 1 100.00
uart_csr_aliasing 0.820s 207.386us 1 1 100.00
uart_same_csr_outstanding 0.760s 20.577us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 38.536us 1 1 100.00
uart_csr_rw 0.630s 47.613us 1 1 100.00
uart_csr_aliasing 0.820s 207.386us 1 1 100.00
uart_same_csr_outstanding 0.760s 20.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.960s 41.334us 1 1 100.00
uart_tl_intg_err 1.170s 260.538us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.170s 260.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 46.950s 8472.894us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 85711107532304891559500326533583491934700501121496435229548275134407623540794 78
UVM_ERROR @ 3026527526 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3287592642 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 3287592642 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 3290138965 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0