Simulation Results: aes/masked

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.20 %
  • code
  • 95.05 %
  • assert
  • 98.43 %
  • func
  • 65.12 %
  • block
  • 95.67 %
  • line
  • 97.42 %
  • branch
  • 89.26 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 101.897us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 111.595us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 59.149us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 67.457us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 800.798us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 1328.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 74.822us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 67.457us 1 1 100.00
aes_csr_aliasing 3.000s 1328.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 111.595us 1 1 100.00
aes_config_error 2.000s 74.723us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 111.595us 1 1 100.00
aes_config_error 2.000s 74.723us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
back2back 2 2 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_b2b 8.000s 1604.529us 1 1 100.00
backpressure 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 111.595us 1 1 100.00
aes_config_error 2.000s 74.723us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 126.141us 1 1 100.00
aes_config_error 2.000s 74.723us 1 1 100.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 171.986us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 338.138us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 292.851us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
stress 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
sideload 2 2 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_sideload 10.000s 491.753us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 330.876us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 23.000s 10061.371us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 80.639us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 52.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 214.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 214.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.149us 1 1 100.00
aes_csr_rw 2.000s 67.457us 1 1 100.00
aes_csr_aliasing 3.000s 1328.967us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 59.149us 1 1 100.00
aes_csr_rw 2.000s 67.457us 1 1 100.00
aes_csr_aliasing 3.000s 1328.967us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 10.000s 379.775us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 85.532us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 605.131us 1 1 100.00
aes_tl_intg_err 2.000s 112.564us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 112.564us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 111.595us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
aes_core_fi 28.000s 10007.021us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 80.639us 1 1 100.00
aes_config_error 2.000s 74.723us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_core_fi 28.000s 10007.021us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.975us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 59.090us 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 7.000s 764.929us 1 1 100.00
aes_sideload 10.000s 491.753us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.090us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.090us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 59.090us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 59.090us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 59.090us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 7.000s 764.929us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 17.000s 10056.618us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 17.000s 10056.618us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 17.000s 10056.618us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 17.000s 10056.618us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 16.000s 10075.522us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_ctr_fi 2.000s 72.423us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 17.000s 10056.618us 0 1 0.00
aes_ghash_fi 2.000s 119.124us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 17.000s 10056.618us 0 1 0.00
aes_control_fi 2.000s 158.512us 1 1 100.00
aes_cipher_fi 2.000s 58.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 20.557us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 48866873470794502778937755238887818043287570486919160780560269159923479895110 1052
UVM_INFO @ 10075521539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 74814351946384720726157256404710932660730318577465769155437106245778423214894 1731
UVM_INFO @ 10061370668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 7112550501892294932164652508373049261006272268689056209146335510051575040023 3396
UVM_INFO @ 10056618382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 3724416305604506332088947197882115423753934979944541418255219133015451447197 140
UVM_INFO @ 10007020688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 64318135528013069507671793472311699694031474662264607820381927718366432543717 149
UVM_INFO @ 20556892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---