Simulation Results: aes/unmasked

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.39 %
  • code
  • 91.44 %
  • assert
  • 97.75 %
  • func
  • 66.98 %
  • block
  • 91.10 %
  • line
  • 93.30 %
  • branch
  • 83.68 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 131.001us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 81.062us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 58.261us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.385us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 4700.403us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 129.844us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 70.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.385us 1 1 100.00
aes_csr_aliasing 3.000s 129.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 81.062us 1 1 100.00
aes_config_error 2.000s 69.504us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 81.062us 1 1 100.00
aes_config_error 2.000s 69.504us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_b2b 2.000s 63.734us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 81.062us 1 1 100.00
aes_config_error 2.000s 69.504us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 64.990us 1 1 100.00
aes_config_error 2.000s 69.504us 1 1 100.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 296.683us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 190.185us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 208.145us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_sideload 2.000s 100.635us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 128.108us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 4.000s 208.522us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 135.275us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 168.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 2218.610us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 2218.610us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.261us 1 1 100.00
aes_csr_rw 2.000s 62.385us 1 1 100.00
aes_csr_aliasing 3.000s 129.844us 1 1 100.00
aes_same_csr_outstanding 2.000s 273.350us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 58.261us 1 1 100.00
aes_csr_rw 2.000s 62.385us 1 1 100.00
aes_csr_aliasing 3.000s 129.844us 1 1 100.00
aes_same_csr_outstanding 2.000s 273.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 125.777us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 309.967us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 793.846us 1 1 100.00
aes_tl_intg_err 2.000s 351.275us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 351.275us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 81.062us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
aes_core_fi 2.000s 106.208us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 135.275us 1 1 100.00
aes_config_error 2.000s 69.504us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_core_fi 2.000s 106.208us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 127.273us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 82.642us 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 101.842us 1 1 100.00
aes_sideload 2.000s 100.635us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.642us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 82.642us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 82.642us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 82.642us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 82.642us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 101.842us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 29.000s 10037.766us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 29.000s 10037.766us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 29.000s 10037.766us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 29.000s 10037.766us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 9.000s 10177.825us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_ctr_fi 2.000s 239.760us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 29.000s 10037.766us 0 1 0.00
aes_ghash_fi 2.000s 48.991us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 29.000s 10037.766us 0 1 0.00
aes_control_fi 2.000s 74.590us 1 1 100.00
aes_cipher_fi 2.000s 52.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 7.056us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 25746771895273091805421930481815215978492228001851076962519203907110304649102 4165
UVM_INFO @ 10177824580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 52540358250132091976299464173142763902755845573701822442245922224561646372684 2947
UVM_INFO @ 10037766182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 90807834581429568774557296768656704704194856151754005403183670694919496607669 147
UVM_INFO @ 7055855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---