Simulation Results: clkmgr

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.59 %
  • code
  • 69.59 %
  • assert
  • 88.64 %
  • func
  • 71.54 %
  • line
  • 82.21 %
  • branch
  • 87.42 %
  • cond
  • 78.50 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.820s 22.522us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.930s 38.965us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.630s 1.924us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.910s 22.884us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.600s 104.815us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
clkmgr_csr_aliasing 0.910s 22.884us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.960s 43.028us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.890s 26.365us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.040s 43.909us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.820s 22.522us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.800s 10.241us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.860s 25.403us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.800s 10.241us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 4.080s 420.246us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 16.966us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.640s 385.280us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.640s 385.280us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.930s 38.965us 1 1 100.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
clkmgr_csr_aliasing 0.910s 22.884us 0 1 0.00
clkmgr_same_csr_outstanding 0.920s 43.568us 1 1 100.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.930s 38.965us 1 1 100.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
clkmgr_csr_aliasing 0.910s 22.884us 0 1 0.00
clkmgr_same_csr_outstanding 0.920s 43.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.370s 409.106us 1 1 100.00
clkmgr_tl_intg_err 1.200s 64.300us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.420s 210.993us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.420s 210.993us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.420s 210.993us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.420s 210.993us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.680s 9.286us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.200s 64.300us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.800s 10.241us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.860s 25.403us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.420s 210.993us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.890s 24.850us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.370s 409.106us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.255us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.370s 409.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.610s 2.262us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.110s 19.319us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 106740668679597484466162833608595233830701870296359423264494916502020107303864 75
UVM_INFO @ 10241018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 26873488610311200892800091374327393447258232694393852183103597253179782537080 78
UVM_INFO @ 25402929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 77054131571667667615570423126277244754892361837061289016243647140903772929559 79
UVM_INFO @ 19318725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 93811486603274242051317755977655285013835919685548285223587918152888808810151 98
UVM_INFO @ 420246185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 650778145206821465672601826089701407382321733290662391959898469773401060001 74
UVM_INFO @ 2262440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 61012402387912962020198651545884166237882813982636850681319854355413421775757 75
UVM_INFO @ 9286371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 15147563354098027685249520737360817058752897545797067750661133839406231644179 126
UVM_INFO @ 64299578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 20388652669812455460900145956745448420115651151938781669413856236511312879066 75
UVM_INFO @ 2254743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 20104496211167230425632322273379214712112517942924715107857859198382131733931 75
UVM_INFO @ 22884302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 18071959064881352653664323616993288594840110639818442775869320992477974204179 75
UVM_INFO @ 1923873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---