Simulation Results: dma

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.31 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 61.75 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 701.108us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 549.744us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 2102.786us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 18.568us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 31.062us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 2073.330us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 2427.495us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 75.092us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 31.062us 1 1 100.00
dma_csr_aliasing 3.000s 2427.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 20.000s 11484.699us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 686.000s 296715.329us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 130.000s 10569.506us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 130.000s 10569.506us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 686.000s 296715.329us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 94.000s 15371.886us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 130.000s 10569.506us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 14.000s 2114.094us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 214.000s 19861.677us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 45.832us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 37.281us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 257.478us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 257.478us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.568us 1 1 100.00
dma_csr_rw 2.000s 31.062us 1 1 100.00
dma_csr_aliasing 3.000s 2427.495us 1 1 100.00
dma_same_csr_outstanding 2.000s 109.616us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 18.568us 1 1 100.00
dma_csr_rw 2.000s 31.062us 1 1 100.00
dma_csr_aliasing 3.000s 2427.495us 1 1 100.00
dma_same_csr_outstanding 2.000s 109.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 1458.704us 1 1 100.00
dma_generic_stress 94.000s 15371.886us 1 1 100.00
dma_handshake_stress 130.000s 10569.506us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1356.777us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 109.742us 1 1 100.00
dma_sec_cm 2.000s 12.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 98.000s 10492.371us 1 1 100.00
dma_longer_transfer 3.000s 162.476us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 107.170us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 103582792587022936888269760174075107559300619386168894803703241474550985067494 94
UVM_INFO @ 107169702ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---