Simulation Results: edn/edn0

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.21 %
  • code
  • 78.19 %
  • assert
  • 93.49 %
  • func
  • 80.95 %
  • line
  • 96.41 %
  • branch
  • 87.31 %
  • cond
  • 83.81 %
  • toggle
  • 76.66 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 22.160us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 14.773us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 26.856us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.790s 265.242us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 231.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 223.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 26.856us 1 1 100.00
edn_csr_aliasing 1.120s 231.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.250s 36.644us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.250s 36.644us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.250s 36.644us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.190s 22.781us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 108.446us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 35.179us 1 1 100.00
disable 2 2 100.00
edn_disable 0.920s 22.314us 1 1 100.00
edn_disable_auto_req_mode 1.070s 61.108us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.280s 396.866us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.940s 25.419us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 20.837us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.650s 57.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.650s 57.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 14.773us 1 1 100.00
edn_csr_rw 0.850s 26.856us 1 1 100.00
edn_csr_aliasing 1.120s 231.393us 1 1 100.00
edn_same_csr_outstanding 0.920s 36.984us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 14.773us 1 1 100.00
edn_csr_rw 0.850s 26.856us 1 1 100.00
edn_csr_aliasing 1.120s 231.393us 1 1 100.00
edn_same_csr_outstanding 0.920s 36.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
edn_tl_intg_err 1.940s 493.202us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 49.455us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 108.446us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 108.446us 1 1 100.00
edn_sec_cm 6.690s 830.765us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 108.446us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.940s 493.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 69.500s 16320.800us 1 1 100.00