Simulation Results: edn/edn1

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 84.52 %
  • assert
  • 97.14 %
  • func
  • 82.35 %
  • line
  • 98.33 %
  • branch
  • 93.51 %
  • cond
  • 90.54 %
  • toggle
  • 95.89 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.730s 45.739us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.760s 62.039us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 167.347us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.510s 913.414us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.110s 38.616us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.930s 74.476us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 167.347us 1 1 100.00
edn_csr_aliasing 1.110s 38.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.050s 47.168us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.050s 47.168us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.050s 47.168us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.710s 34.504us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.900s 62.654us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 56.130us 1 1 100.00
disable 2 2 100.00
edn_disable 0.710s 12.498us 1 1 100.00
edn_disable_auto_req_mode 0.960s 128.963us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.190s 838.001us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 12.843us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 32.534us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.540s 391.674us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.540s 391.674us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.760s 62.039us 1 1 100.00
edn_csr_rw 0.820s 167.347us 1 1 100.00
edn_csr_aliasing 1.110s 38.616us 1 1 100.00
edn_same_csr_outstanding 0.980s 57.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.760s 62.039us 1 1 100.00
edn_csr_rw 0.820s 167.347us 1 1 100.00
edn_csr_aliasing 1.110s 38.616us 1 1 100.00
edn_same_csr_outstanding 0.980s 57.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
edn_tl_intg_err 1.230s 381.999us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 16.023us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.900s 62.654us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.900s 62.654us 1 1 100.00
edn_sec_cm 3.730s 657.515us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.900s 62.654us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.230s 381.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 74.700s 8850.905us 1 1 100.00