Simulation Results: hmac

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.05 %
  • code
  • 98.47 %
  • assert
  • 96.70 %
  • func
  • 44.98 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.29 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.090s 527.197us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.990s 78.476us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.880s 19.748us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.870s 3139.485us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.410s 111.254us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.490s 20.747us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.880s 19.748us 1 1 100.00
hmac_csr_aliasing 4.410s 111.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 86.800s 6719.813us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 62.570s 9407.814us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.860s 2323.171us 1 1 100.00
hmac_test_sha384_vectors 19.490s 201.228us 1 1 100.00
hmac_test_sha512_vectors 375.720s 40977.291us 1 1 100.00
hmac_test_hmac256_vectors 6.410s 528.944us 1 1 100.00
hmac_test_hmac384_vectors 8.310s 259.286us 1 1 100.00
hmac_test_hmac512_vectors 9.740s 1056.839us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.510s 684.801us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 429.540s 14412.801us 1 1 100.00
error 1 1 100.00
hmac_error 6.160s 397.336us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 108.700s 10756.157us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.090s 527.197us 1 1 100.00
hmac_long_msg 86.800s 6719.813us 1 1 100.00
hmac_back_pressure 62.570s 9407.814us 1 1 100.00
hmac_datapath_stress 429.540s 14412.801us 1 1 100.00
hmac_burst_wr 15.510s 684.801us 1 1 100.00
hmac_stress_all 783.850s 19739.946us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.090s 527.197us 1 1 100.00
hmac_long_msg 86.800s 6719.813us 1 1 100.00
hmac_back_pressure 62.570s 9407.814us 1 1 100.00
hmac_datapath_stress 429.540s 14412.801us 1 1 100.00
hmac_wipe_secret 108.700s 10756.157us 1 1 100.00
hmac_test_sha256_vectors 9.860s 2323.171us 1 1 100.00
hmac_test_sha384_vectors 19.490s 201.228us 1 1 100.00
hmac_test_sha512_vectors 375.720s 40977.291us 1 1 100.00
hmac_test_hmac256_vectors 6.410s 528.944us 1 1 100.00
hmac_test_hmac384_vectors 8.310s 259.286us 1 1 100.00
hmac_test_hmac512_vectors 9.740s 1056.839us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.090s 527.197us 1 1 100.00
hmac_long_msg 86.800s 6719.813us 1 1 100.00
hmac_back_pressure 62.570s 9407.814us 1 1 100.00
hmac_datapath_stress 429.540s 14412.801us 1 1 100.00
hmac_burst_wr 15.510s 684.801us 1 1 100.00
hmac_error 6.160s 397.336us 1 1 100.00
hmac_wipe_secret 108.700s 10756.157us 1 1 100.00
hmac_test_sha256_vectors 9.860s 2323.171us 1 1 100.00
hmac_test_sha384_vectors 19.490s 201.228us 1 1 100.00
hmac_test_sha512_vectors 375.720s 40977.291us 1 1 100.00
hmac_test_hmac256_vectors 6.410s 528.944us 1 1 100.00
hmac_test_hmac384_vectors 8.310s 259.286us 1 1 100.00
hmac_test_hmac512_vectors 9.740s 1056.839us 1 1 100.00
hmac_stress_all 783.850s 19739.946us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 783.850s 19739.946us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 26.270us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.730s 16.133us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.370s 60.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.370s 60.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.990s 78.476us 1 1 100.00
hmac_csr_rw 0.880s 19.748us 1 1 100.00
hmac_csr_aliasing 4.410s 111.254us 1 1 100.00
hmac_same_csr_outstanding 2.700s 49.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.990s 78.476us 1 1 100.00
hmac_csr_rw 0.880s 19.748us 1 1 100.00
hmac_csr_aliasing 4.410s 111.254us 1 1 100.00
hmac_same_csr_outstanding 2.700s 49.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.390s 1427.547us 1 1 100.00
hmac_tl_intg_err 4.710s 236.677us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.710s 236.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.090s 527.197us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.670s 104.714us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 173.410s 4878.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.390s 60.158us 1 1 100.00