Simulation Results

Simulation Results: i2c

30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.73 %

code
81.87 %

assert
96.19 %

func
82.14 %

line
96.75 %

branch
92.69 %

cond
85.01 %

toggle
89.66 %

FSM
45.24 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	52.680s	1607.512us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.000s	1616.942us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.760s	18.477us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.800s	21.774us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.290s	701.608us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.960s	160.335us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.910s	133.939us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.800s	21.774us	1	1	100.00
	i2c_csr_aliasing	1.960s	160.335us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.960s	21.812us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	12.750s	2132.637us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	100.960s	50042.767us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.660s	41.403us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	116.220s	2874.265us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	49.330s	24105.401us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.340s	802.602us	1	1	100.00
	i2c_host_fifo_fmt_empty	10.400s	279.809us	1	1	100.00
	i2c_host_fifo_reset_rx	5.010s	1303.345us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	34.810s	1945.470us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.530s	1401.443us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.970s	3.944us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.220s	426.280us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	21.650s	5453.373us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.200s	984.629us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	21.020s	1766.871us	1	1	100.00
	i2c_target_intr_smoke	4.250s	5701.878us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.330s	181.266us	1	1	100.00
	i2c_target_fifo_reset_tx	0.800s	314.378us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	477.410s	47797.673us	1	1	100.00
	i2c_target_stress_rd	21.020s	1766.871us	1	1	100.00
	i2c_target_intr_stress_wr	74.300s	9495.537us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.550s	1098.438us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	12.540s	4072.790us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.020s	666.611us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.820s	1080.458us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.500s	521.343us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.900s	102.028us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	100.960s	50042.767us	1	1	100.00
	i2c_host_perf_precise	1.890s	235.238us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.530s	1401.443us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.510s	140.249us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.800s	633.934us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.870s	437.673us	1	1	100.00
	i2c_target_nack_txstretch	1.140s	300.199us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	15.250s	529.273us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.510s	2074.948us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.970s	51.945us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.870s	44.575us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.170s	31.927us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.170s	31.927us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	18.477us	1	1	100.00
	i2c_csr_rw	0.800s	21.774us	1	1	100.00
	i2c_csr_aliasing	1.960s	160.335us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	64.250us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.760s	18.477us	1	1	100.00
	i2c_csr_rw	0.800s	21.774us	1	1	100.00
	i2c_csr_aliasing	1.960s	160.335us	1	1	100.00
	i2c_same_csr_outstanding	0.940s	64.250us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.100s	510.183us	1	1	100.00
	i2c_sec_cm	1.070s	46.462us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.100s	510.183us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	15.280s	1689.128us	1
target_error_intr				1
	i2c_target_unexp_stop	1.110s	77.588us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.550s	2642.569us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	45004125333326577803777689594132809339359678696835115998264023380325111016976	80	UVM_INFO @ 21812360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	101380262603086632344038362918063794646666915510410783119079078379151744412744	93	UVM_INFO @ 2132636588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	57590710579588118506971147549604303846063561151319105299023557937408219828190	81	UVM_INFO @ 3944332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	49653061300899496411219564912572705938383801160231830136571920967409516626237	84	UVM_INFO @ 426280337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	2034761156625438273989170301286618442949932481238533943268781708253468539128	78	UVM_INFO @ 77587928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	19719740059098831458203749853795173584933270538376459780272948700887504332102	98	UVM_INFO @ 1689127993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	21803904974175672121338786338526729108891409133948212730610087364980108743640	85	UVM_INFO @ 2642569150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---