Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.92 %
  • code
  • 84.32 %
  • assert
  • 95.99 %
  • func
  • 92.45 %
  • line
  • 97.74 %
  • branch
  • 96.13 %
  • cond
  • 79.34 %
  • toggle
  • 84.77 %
  • FSM
  • 63.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.400s 50.259us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.080s 18.248us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 15.314us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 104.084us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 35.437us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.180s 25.938us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 15.314us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 35.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.350s 87.648us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.130s 498.602us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 52.825us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.830s 100.259us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.480s 465.424us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_prog_failure 1.830s 100.259us 1 1 100.00
lc_ctrl_errors 10.480s 465.424us 1 1 100.00
lc_ctrl_security_escalation 5.510s 1659.170us 1 1 100.00
lc_ctrl_jtag_state_failure 29.630s 3406.577us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.810s 817.513us 1 1 100.00
lc_ctrl_jtag_errors 13.670s 1463.013us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.370s 663.980us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.430s 1889.678us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.810s 817.513us 1 1 100.00
lc_ctrl_jtag_errors 13.670s 1463.013us 1 1 100.00
lc_ctrl_jtag_access 4.740s 2899.607us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.480s 6420.417us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.410s 56.597us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.140s 67.811us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.610s 753.936us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.250s 919.136us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.510s 18.470us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.780s 89.635us 1 1 100.00
lc_ctrl_jtag_alert_test 0.950s 158.723us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.510s 1337.909us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.760s 37.997us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 65.210s 70397.274us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.360s 19.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.670s 594.662us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.670s 594.662us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 18.248us 1 1 100.00
lc_ctrl_csr_rw 0.830s 15.314us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 35.437us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 18.494us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.080s 18.248us 1 1 100.00
lc_ctrl_csr_rw 0.830s 15.314us 1 1 100.00
lc_ctrl_csr_aliasing 1.040s 35.437us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.470s 18.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
lc_ctrl_tl_intg_err 1.710s 126.975us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.710s 126.975us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.130s 498.602us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.990s 2896.177us 1 1 100.00
lc_ctrl_sec_cm 6.140s 150.650us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.510s 1659.170us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.350s 87.648us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.430s 1889.678us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.120s 413.247us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.120s 413.247us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.950s 271.907us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.650s 1029.081us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.650s 1029.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.190s 275.712us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 1150384897660519091119902368501731050523291776525879648862279634413994781470 251
UVM_INFO @ 275712485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---