Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 85.47 %
  • assert
  • 95.99 %
  • func
  • 93.17 %
  • line
  • 97.71 %
  • branch
  • 96.01 %
  • cond
  • 79.71 %
  • toggle
  • 86.64 %
  • FSM
  • 67.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.620s 69.497us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.870s 71.782us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 54.491us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 50.817us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 50.610us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.850s 35.943us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 54.491us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 50.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.580s 67.595us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.770s 2657.898us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 14.216us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.470s 157.052us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.500s 9867.659us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_prog_failure 1.470s 157.052us 1 1 100.00
lc_ctrl_errors 9.500s 9867.659us 1 1 100.00
lc_ctrl_security_escalation 4.720s 1099.856us 1 1 100.00
lc_ctrl_jtag_state_failure 18.810s 1559.520us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.520s 380.556us 1 1 100.00
lc_ctrl_jtag_errors 52.840s 3048.515us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.290s 645.373us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.200s 3694.476us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.520s 380.556us 1 1 100.00
lc_ctrl_jtag_errors 52.840s 3048.515us 1 1 100.00
lc_ctrl_jtag_access 6.460s 357.100us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.240s 10478.402us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.010s 154.464us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.470s 250.775us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.700s 1213.992us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 13.920s 3136.451us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.290s 30.342us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.110s 52.440us 1 1 100.00
lc_ctrl_jtag_alert_test 1.280s 428.644us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.560s 514.497us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 90.043us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 76.930s 3917.348us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 48.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.270s 1079.798us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.270s 1079.798us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 71.782us 1 1 100.00
lc_ctrl_csr_rw 0.780s 54.491us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 50.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 36.973us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 71.782us 1 1 100.00
lc_ctrl_csr_rw 0.780s 54.491us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 50.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 36.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 143.813us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 143.813us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.770s 2657.898us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.790s 146.427us 1 1 100.00
lc_ctrl_sec_cm 6.180s 877.277us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.720s 1099.856us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.580s 67.595us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.200s 3694.476us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.250s 483.699us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.250s 483.699us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.510s 405.999us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.040s 2572.768us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.040s 2572.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 35.240s 4162.731us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 25147891405789575694461214126655003757745363526712707955755820449251049701608 2623
UVM_INFO @ 4162731025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---