| V1 |
|
83.33% |
| V2 |
|
72.73% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 78.000s | 13391.331us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 34.924us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 28.917us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 71.075us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 124.654us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 3.890us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 28.917us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 124.654us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 2.000s | 30.175us | 0 | 1 | 0.00 | |
| mbx_max_activity | 0 | 1 | 0.00 | |||
| mbx_stress_zero_delays | 4.000s | 253.966us | 0 | 1 | 0.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 27.000s | 9419.655us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 18.000s | 1484.233us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 29.920us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 27.726us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 6.758us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 1.000s | 6.758us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 34.924us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 28.917us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 124.654us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 57.500us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 34.924us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 28.917us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 124.654us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 57.500us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 2.000s | 721.653us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 39.612us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | ||||
| mbx_stress | 85788711102471624446733751684662739760699829914835342140037976752871129532157 | 89 |
UVM_INFO @ 30174577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_stress_zero_delays | 70348760323706216477110100808587761973405927372771846155460154623695322017497 | 109 |
UVM_INFO @ 253965750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | ||||
| mbx_tl_errors | 67329454688823897687716100279445107347371982074368135554692340274155289213856 | 85 |
TL item was: req: (cip_tl_seq_item@16341) { a_addr: 'h64567f50 a_data: 'h4ec79997 a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'hb0 a_opcode: 'h1 a_user: 'h248fa d_param: 'h0 d_source: 'hb0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6758260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_csr_mem_rw_with_rand_reset | 27905084386564015665808274159743300365754005147607813032217517576665397123875 | 86 |
TL item was: req: (cip_tl_seq_item@18838) { a_addr: 'hcca19ab0 a_data: 'h67971d1 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'hc6 a_opcode: 'h1 a_user: 'h26130 d_param: 'h0 d_source: 'hc6 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3889709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|