Simulation Results: otbn

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.42 %
  • code
  • 95.27 %
  • assert
  • 89.67 %
  • func
  • 95.34 %
  • block
  • 99.39 %
  • line
  • 99.57 %
  • branch
  • 92.29 %
  • toggle
  • 91.76 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 40.981us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 11.000s 60.563us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.018us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 283.748us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 43.935us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 4.000s 126.843us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.018us 1 1 100.00
otbn_csr_aliasing 3.000s 43.935us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 47.000s 528.033us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 36.000s 4205.807us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 31.000s 123.958us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 43.000s 156.978us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 34.000s 262.413us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 54.000s 309.234us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 19.210us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 15.141us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 90.929us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 46.555us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 23.212us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 61.836us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 61.836us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 11.000s 60.563us 1 1 100.00
otbn_csr_rw 4.000s 14.018us 1 1 100.00
otbn_csr_aliasing 3.000s 43.935us 1 1 100.00
otbn_same_csr_outstanding 4.000s 12.455us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 11.000s 60.563us 1 1 100.00
otbn_csr_rw 4.000s 14.018us 1 1 100.00
otbn_csr_aliasing 3.000s 43.935us 1 1 100.00
otbn_same_csr_outstanding 4.000s 12.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 35.132us 1 1 100.00
otbn_dmem_err 6.000s 91.526us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 97.607us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 62.231us 1 1 100.00
otbn_mac_bignum_acc_err 5.000s 680.766us 1 1 100.00
otbn_urnd_err 5.000s 10.220us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 28.116us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 38.007us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 9.855us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
otbn_tl_intg_err 8.000s 234.638us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 20.000s 599.748us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 40.981us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 91.526us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 35.132us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 8.000s 234.638us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 19.210us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 35.132us 1 1 100.00
otbn_dmem_err 6.000s 91.526us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 15.141us 0 1 0.00
otbn_illegal_mem_acc 6.000s 28.116us 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 35.132us 1 1 100.00
otbn_dmem_err 6.000s 91.526us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 15.141us 0 1 0.00
otbn_illegal_mem_acc 6.000s 28.116us 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 19.210us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 35.132us 1 1 100.00
otbn_dmem_err 6.000s 91.526us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 15.141us 0 1 0.00
otbn_illegal_mem_acc 6.000s 28.116us 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 11.614us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 19.374us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 16.000s 662.636us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 16.000s 662.636us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 24.165us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 66.923us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 18.574us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 18.574us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 13.767us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 34.000s 262.413us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 5.000s 30.540us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 35.860us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 92.000s 489.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 132.000s 1319.002us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 71.769us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 42149804054350644815039739806882976444484972195720797243304032779846995842985 330
UVM_INFO @ 1319001722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 104887487354084181058181587421380754056382483863765225449673820097041776208361 105
UVM_INFO @ 15141399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 58454119680559985447800001766171724981351112778548752486027834098700098889897 106
UVM_INFO @ 10219512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---