Simulation Results: otp_ctrl

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.88 %
  • code
  • 70.91 %
  • assert
  • 93.08 %
  • func
  • 51.64 %
  • line
  • 87.50 %
  • branch
  • 83.63 %
  • cond
  • 85.50 %
  • toggle
  • 62.03 %
  • FSM
  • 35.91 %
Validation stages
V1
100.00%
V2
55.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.850s 823.303us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.900s 243.199us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.770s 95.155us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.690s 257.254us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.410s 173.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.820s 140.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.770s 95.155us 1 1 100.00
otp_ctrl_csr_aliasing 4.410s 173.542us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.620s 78.905us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.410s 548.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 107.480s 2404.356us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.780s 129.068us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 5.310s 260.452us 0 1 0.00
otp_ctrl_check_fail 22.250s 1350.054us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.950s 334.546us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.980s 540.890us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 16.290s 1310.417us 0 1 0.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 36.580s 3759.561us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 14.280s 785.839us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 10.150s 355.163us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 10.930s 1527.070us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.460s 176.112us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.090s 733.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.480s 341.624us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.480s 341.624us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.900s 243.199us 1 1 100.00
otp_ctrl_csr_rw 1.770s 95.155us 1 1 100.00
otp_ctrl_csr_aliasing 4.410s 173.542us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.330s 63.201us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.900s 243.199us 1 1 100.00
otp_ctrl_csr_rw 1.770s 95.155us 1 1 100.00
otp_ctrl_csr_aliasing 4.410s 173.542us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.330s 63.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
otp_ctrl_tl_intg_err 21.660s 4101.639us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 21.660s 4101.639us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_macro_errs 14.280s 785.839us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_macro_errs 14.280s 785.839us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.690s 329.893us 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.780s 129.068us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 22.250s 1350.054us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 18.970s 3886.814us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 263.300s 16337.652us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.950s 334.546us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 11.570s 867.215us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 14.280s 785.839us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 69.110s 59095.852us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.420s 122.989us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_partition_walk 51147479425885940417011314458479879703416534339209248421320221771701804513523 165605
UVM_INFO @ 2404356153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 40996779586568394187591197169841769226567252678576447557220541963245231554527 4768
UVM_INFO @ 334545781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 94989736462767285666866752130701409014381509009410433409632839160130856954644 89
UVM_INFO @ 59095851705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 81613122682101783840428469542813941358541216641104139313442576005561665485612 3804
UVM_INFO @ 260451550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_parallel_lc_req 57474615273076254840570362742354320260739412285507234555916018743271336946817 13737
UVM_INFO @ 1310416898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_dai_lock 115043382132866336739074223097704395486516479443623250723076171689519129167199 14797
UVM_INFO @ 3886813609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 102126663438015849798261694964564422974389429412414264765373245649892450888826 11725
UVM_INFO @ 1527069945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_check_fail 9975725998898296528896300438985460355284815414760300925966257508151679049873 30480
UVM_INFO @ 1350054392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 54366815022024308217973005161076016294491376449593043804096240263940906105520 5728
UVM_INFO @ 785839012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_test_access 76277742463093880709823820572864697154304921181674328874310952370560214701519 13969
UVM_INFO @ 355163272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 21601022642396381188549136442487066609319470541758898674147237145762164038129 91
UVM_INFO @ 122988656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---