Simulation Results: rom_ctrl/64kb

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 96.02 %
  • assert
  • 96.80 %
  • func
  • 94.03 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 96.58 %
  • toggle
  • 99.21 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.670s 1064.685us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.900s 1082.241us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.220s 293.726us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.490s 210.430us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.020s 322.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.870s 419.362us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.220s 293.726us 1 1 100.00
rom_ctrl_csr_aliasing 8.020s 322.804us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.470s 1029.466us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.380s 291.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.750s 310.503us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.140s 1581.522us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.970s 2108.695us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.460s 1139.061us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.880s 377.407us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.880s 377.407us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.900s 1082.241us 1 1 100.00
rom_ctrl_csr_rw 7.220s 293.726us 1 1 100.00
rom_ctrl_csr_aliasing 8.020s 322.804us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.680s 2393.326us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.900s 1082.241us 1 1 100.00
rom_ctrl_csr_rw 7.220s 293.726us 1 1 100.00
rom_ctrl_csr_aliasing 8.020s 322.804us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.680s 2393.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.910s 6104.822us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
rom_ctrl_tl_intg_err 51.730s 1378.423us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.670s 1064.685us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.670s 1064.685us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.670s 1064.685us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.730s 1378.423us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
rom_ctrl_kmac_err_chk 14.970s 2108.695us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.650s 2474.550us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.910s 6104.822us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 436.880s 771.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 9.360s 336.322us 1 1 100.00