Simulation Results: rstmgr

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.83 %
  • code
  • 99.24 %
  • assert
  • 97.25 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.52 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.310s 64.066us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.370s 92.030us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.400s 195.998us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.500s 44.779us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.440s 100.402us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00
rstmgr_csr_aliasing 1.500s 44.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.710s 196.744us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.910s 41.814us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.200s 96.079us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.550s 733.384us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.550s 733.384us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.550s 733.384us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.550s 733.384us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 17.490s 2804.855us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 38.801us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.430s 55.010us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.430s 55.010us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.370s 92.030us 1 1 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00
rstmgr_csr_aliasing 1.500s 44.779us 1 1 100.00
rstmgr_same_csr_outstanding 1.550s 66.614us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.370s 92.030us 1 1 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00
rstmgr_csr_aliasing 1.500s 44.779us 1 1 100.00
rstmgr_same_csr_outstanding 1.550s 66.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.150s 3537.594us 1 1 100.00
rstmgr_tl_intg_err 5.440s 616.521us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.150s 3537.594us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.150s 3537.594us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.440s 616.521us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.100s 65.144us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.230s 469.133us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.020s 293.585us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.150s 3537.594us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 36.751us 1 1 100.00