Simulation Results: rv_dm/use_dmi_interface

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.88 %
  • code
  • 72.82 %
  • assert
  • 96.01 %
  • func
  • 49.82 %
  • line
  • 90.27 %
  • branch
  • 74.36 %
  • cond
  • 75.91 %
  • toggle
  • 70.46 %
  • FSM
  • 53.12 %
Validation stages
V1
96.30%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.810s 2281.883us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.880s 508.710us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.900s 155.577us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 9.610s 7764.809us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 0.770s 254.741us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 1.470s 4052.166us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 2.260s 3125.735us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 43.320s 58539.737us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 380.650s 217448.043us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.970s 611.641us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.870s 186.724us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.040s 199.222us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.800s 148.110us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.720s 319.849us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.350s 568.137us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.100s 84.257us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.710s 1356.632us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.970s 611.641us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.970s 123.264us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.420s 373.616us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.040s 199.222us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.850s 79.855us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.240s 167.168us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.870s 104.725us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 41.640s 17502.136us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 17.580s 2245.325us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.290s 202.616us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 17.580s 2245.325us 1 1 100.00
rv_dm_csr_rw 1.870s 104.725us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.770s 108.562us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.660s 106.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.810s 2281.883us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 0.790s 145.584us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.760s 113.341us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.850s 353.617us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.310s 1256.303us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 2.410s 3199.261us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 1.150s 114.756us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 0.850s 213.208us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 6.220s 10308.406us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.910s 80.124us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 0.880s 781.366us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.780s 490.815us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.840s 113.138us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 15.520s 8579.211us 1 1 100.00
rv_dm_tap_fsm_rand_reset 57.080s 7013.176us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.730s 89.203us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.740s 82.849us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.880s 62.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 2.010s 128.637us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 2.010s 128.637us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 17.580s 2245.325us 1 1 100.00
rv_dm_csr_hw_reset 1.240s 167.168us 1 1 100.00
rv_dm_csr_rw 1.870s 104.725us 1 1 100.00
rv_dm_same_csr_outstanding 5.370s 2379.819us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 17.580s 2245.325us 1 1 100.00
rv_dm_csr_hw_reset 1.240s 167.168us 1 1 100.00
rv_dm_csr_rw 1.870s 104.725us 1 1 100.00
rv_dm_same_csr_outstanding 5.370s 2379.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 1.950s 479.820us 1 1 100.00
rv_dm_tl_intg_err 10.330s 1563.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 10.330s 1563.256us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 0.880s 781.366us 1 1 100.00
rv_dm_debug_disabled 1.010s 136.605us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 0.880s 781.366us 1 1 100.00
rv_dm_debug_disabled 1.010s 136.605us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.810s 2281.883us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 0.880s 223.081us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.940s 128.852us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.940s 128.852us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 0.880s 223.081us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 4.790s 1397.233us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 307.400s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:
rv_dm_sba_tl_access 36231423386177791837987554400676951761394425092420459232419231814079504881152 86
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5323
rv_dm_autoincr_sba_tl_access 92750705455825032782955568294400694970471724809118482612994870910621231422842 122
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @21189
Error-[CNST-CIF] Constraints inconsistency failure
rv_dm_delayed_resp_sba_tl_access 70757752509057342163737943005773762004047659428839565199014264383633112132520 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
rv_dm_bad_sba_tl_access 15251792129541518938876493896491473868586472386592584980182993833878703982947 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 16872091144937239749628369449814225948307627070290276064371532447855543620815 77
UVM_INFO @ 148109730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 34019943729526275695878512110755654815866032984708967070532990385051323744196 77
UVM_INFO @ 113138144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 60656474456329893359685445157281653744935135287948496825280238752155357925520 84
UVM_INFO @ 1397233335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 25430965261426317286826536140439030142468886012502966422323712886837168993487 77
UVM_INFO @ 80124268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 46916659699475837583928047739737195495978509016793891360660380140439325758843 78
UVM_INFO @ 82848801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])
rv_dm_buffered_enable 3353238126477623467849587635791504461998235157930077411452500226958384968419 88
UVM_INFO @ 223080735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_scanmode 8323374403657895345389906691222507924727708924867923499541820421052636375465 77
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---