Simulation Results: rv_timer

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.39 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 92.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.610s 45.938us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 16.912us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.640s 34.205us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.740s 1638.603us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.050s 17.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.780s 59.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.640s 34.205us 1 1 100.00
rv_timer_csr_aliasing 1.050s 17.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.910s 1316.462us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.850s 1365.923us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 115.340s 289663.975us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 115.340s 289663.975us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.630s 939.359us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.620s 14.280us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 18.127us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.050s 586.942us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.050s 586.942us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 16.912us 1 1 100.00
rv_timer_csr_rw 0.640s 34.205us 1 1 100.00
rv_timer_csr_aliasing 1.050s 17.319us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 41.225us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 16.912us 1 1 100.00
rv_timer_csr_rw 0.640s 34.205us 1 1 100.00
rv_timer_csr_aliasing 1.050s 17.319us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 41.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.880s 373.816us 1 1 100.00
rv_timer_tl_intg_err 1.380s 442.488us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.380s 442.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.690s 94.522us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.060s 45.058us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 5.490s 849.652us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 98595333778631532933993312679806518526081711548569341256032083608769093132459 76
UVM_INFO @ 94521974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 84122102148862231475564635643980167081284031718500620233503516129081331015458 75
UVM_INFO @ 1316461767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 106509156070147053567125875751819151490586136435192615632312382270964350453413 75
UVM_INFO @ 45057546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---