Simulation Results: spi_device/1r1w

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.04 %
  • code
  • 93.26 %
  • assert
  • 94.64 %
  • func
  • 61.21 %
  • line
  • 99.05 %
  • branch
  • 98.32 %
  • cond
  • 96.05 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
88.46%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 3.960s 620.667us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 48.363us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.020s 122.789us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 10.780s 3238.755us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.790s 975.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.540s 27.112us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.020s 122.789us 1 1 100.00
spi_device_csr_aliasing 9.790s 975.654us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.810s 19.634us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.910s 253.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.910s 53.881us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.710s 19.966us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.740s 5.172us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.060s 29.129us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.060s 29.129us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.610s 959.213us 1 1 100.00
spi_device_tpm_sts_read 0.820s 320.142us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.710s 12.230us 1 1 100.00
pass_cmd_filtering 1 2 50.00
spi_device_pass_cmd_filtering 4.200s 900.432us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
pass_addr_translation 1 2 50.00
spi_device_pass_addr_payload_swap 1.780s 294.546us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
pass_payload_translation 1 2 50.00
spi_device_pass_addr_payload_swap 1.780s 294.546us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_info_slots 0 1 0.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_read_status 1 2 50.00
spi_device_intercept 4.000s 499.327us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_read_jedec 1 2 50.00
spi_device_intercept 4.000s 499.327us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_read_sfdp 1 2 50.00
spi_device_intercept 4.000s 499.327us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_fast_read 1 2 50.00
spi_device_intercept 4.000s 499.327us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
cmd_read_pipeline 1 2 50.00
spi_device_intercept 4.000s 499.327us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.230s 1602.669us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.500s 414.924us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.500s 414.924us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.500s 414.924us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.070s 330.713us 1 1 100.00
spi_device_read_buffer_direct 4.040s 525.663us 1 1 100.00
cmd_dummy_cycle 1 2 50.00
spi_device_mailbox 5.500s 414.924us 1 1 100.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
quad_spi 0 1 0.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
dual_spi 0 1 0.00
spi_device_flash_all 35.200s 2980.932us 0 1 0.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.050s 111.539us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.050s 111.539us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 3.960s 620.667us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 208.000s 177660.938us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 37.130s 6666.831us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.970s 15.871us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.860s 29.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.860s 114.616us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.860s 114.616us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 48.363us 1 1 100.00
spi_device_csr_rw 2.020s 122.789us 1 1 100.00
spi_device_csr_aliasing 9.790s 975.654us 1 1 100.00
spi_device_same_csr_outstanding 3.360s 211.076us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 48.363us 1 1 100.00
spi_device_csr_rw 2.020s 122.789us 1 1 100.00
spi_device_csr_aliasing 9.790s 975.654us 1 1 100.00
spi_device_same_csr_outstanding 3.360s 211.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.900s 38.313us 1 1 100.00
spi_device_tl_intg_err 12.220s 6674.693us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.220s 6674.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 317.740s 140484.846us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 62042010311269522390238872345143955612795989022127288936294445465738752556183 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 14765829 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 14765829 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 3295884268435707145213807855759659168653075370800050641439954590131729077507 76
UVM_ERROR @ 2579076 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x409e60 [10000001001111001100000] vs 0x0 [0])
UVM_ERROR @ 2624076 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf8c95 [11111000110010010101] vs 0x0 [0])
UVM_ERROR @ 2671076 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x41e2ab [10000011110001010101011] vs 0x0 [0])
UVM_ERROR @ 2740076 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x628c64 [11000101000110001100100] vs 0x0 [0])
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_all 46841045455126926198519887028243179912338425459075119536095912970952824117362 86
tl_ul_fuzzy_flash_status_q[i] = 0x7a68b4
UVM_INFO @ 480763396 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/11
UVM_INFO @ 480763396 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/11
UVM_INFO @ 671974055 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/11