Simulation Results: sram_ctrl/main

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 95.43 %
  • assert
  • 95.91 %
  • func
  • 94.20 %
  • block
  • 94.32 %
  • line
  • 94.88 %
  • branch
  • 90.76 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 366.107us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.984us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.883us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 366.626us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.436us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 359.698us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.883us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.436us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 175.000s 7507.317us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 43.000s 13487.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 5215.140us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 150.000s 5388.726us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 130.000s 39616.763us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 30.000s 13139.520us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 36.000s 44203.465us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 33.000s 16751.789us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 3577.104us 1 1 100.00
sram_ctrl_partial_access_b2b 224.000s 18224.739us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 697.025us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 2659.362us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 1348.534us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 412.841us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1398.183us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 163.000s 63152.841us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 21.534us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 101.096us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 101.096us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.984us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.883us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.436us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.115us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.984us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.883us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.436us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 3839.792us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 184.730us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 184.730us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 412.841us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 412.841us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.883us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 33.000s 16751.789us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.000s 16751.789us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 33.000s 16751.789us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 36.000s 44203.465us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 6.000s 699.006us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 3839.792us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2578.691us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 366.107us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 366.107us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 33.000s 16751.789us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 36.000s 44203.465us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 366.107us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 358.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 50.000s 8300.398us 1 1 100.00