Simulation Results: sram_ctrl/ret

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 83.36 %
  • assert
  • 96.43 %
  • func
  • 91.60 %
  • block
  • 93.80 %
  • line
  • 94.97 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 90.189us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 39.131us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.017us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 99.015us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.331us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 43.263us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.017us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.331us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 91.905us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 101.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 301.891us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 89.000s 6457.529us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 108.530us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 233.773us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 951.608us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 204.870us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 316.577us 1 1 100.00
sram_ctrl_partial_access_b2b 128.000s 10857.165us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 41.994us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 138.088us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 59.352us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 127.772us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 33.612us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 19.000s 1468.350us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 48.146us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 762.912us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 762.912us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.131us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.017us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.331us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.457us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 39.131us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.017us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 56.331us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 16.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 227.915us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 618.403us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 618.403us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 127.772us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 127.772us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.017us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 204.870us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 204.870us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 204.870us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 951.608us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 35.200us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 227.915us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 152.113us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 90.189us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 90.189us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 204.870us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 951.608us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 90.189us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 674.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 19.000s 2429.940us 1 1 100.00