Simulation Results: uart

 
30/04/2026 19:39:18 DVSim: v1.33.0 sha: c776b8b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.42 %
  • code
  • 96.25 %
  • assert
  • 97.12 %
  • func
  • 47.89 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 97.08 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.580s 5804.774us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.570s 32.881us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.730s 32.527us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.020s 816.962us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.780s 121.396us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.650s 37.685us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.730s 32.527us 1 1 100.00
uart_csr_aliasing 0.780s 121.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 47.030s 85533.909us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.580s 5804.774us 1 1 100.00
uart_tx_rx 47.030s 85533.909us 1 1 100.00
parity_error 2 2 100.00
uart_intr 101.400s 106891.265us 1 1 100.00
uart_rx_parity_err 118.200s 98411.369us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 47.030s 85533.909us 1 1 100.00
uart_intr 101.400s 106891.265us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 39.760s 152260.947us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.930s 16675.841us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.630s 32306.027us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 101.400s 106891.265us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 101.400s 106891.265us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 101.400s 106891.265us 1 1 100.00
perf 1 1 100.00
uart_perf 61.030s 22398.580us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.100s 3317.065us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.100s 3317.065us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 55.790s 29579.996us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.200s 3238.907us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 6.350s 13383.248us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.300s 5991.376us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 194.540s 156049.008us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 30.010s 63876.541us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 43.726us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 12.320us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.380s 111.287us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.380s 111.287us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.570s 32.881us 1 1 100.00
uart_csr_rw 0.730s 32.527us 1 1 100.00
uart_csr_aliasing 0.780s 121.396us 1 1 100.00
uart_same_csr_outstanding 1.000s 26.005us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.570s 32.881us 1 1 100.00
uart_csr_rw 0.730s 32.527us 1 1 100.00
uart_csr_aliasing 0.780s 121.396us 1 1 100.00
uart_same_csr_outstanding 1.000s 26.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.320s 831.303us 1 1 100.00
uart_tl_intg_err 0.900s 194.217us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.900s 194.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 10.550s 1119.420us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 94649414195740594435254187663132407098874151762977527650835943020540098700814 75
UVM_ERROR @ 408454232 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1786137088 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1786137088 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2827873652 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/19