Simulation Results: aes/masked

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.01 %
  • code
  • 95.09 %
  • assert
  • 98.29 %
  • func
  • 64.66 %
  • block
  • 95.72 %
  • line
  • 97.32 %
  • branch
  • 89.50 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 75.720us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 152.926us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 119.699us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 133.549us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 123.318us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 76.135us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 260.428us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 133.549us 1 1 100.00
aes_csr_aliasing 2.000s 76.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 152.926us 1 1 100.00
aes_config_error 3.000s 298.605us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 152.926us 1 1 100.00
aes_config_error 3.000s 298.605us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_b2b 7.000s 200.395us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 152.926us 1 1 100.00
aes_config_error 3.000s 298.605us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 70.084us 1 1 100.00
aes_config_error 3.000s 298.605us 1 1 100.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 81.619us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 591.432us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 1069.302us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_sideload 2.000s 66.280us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 199.247us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 56.000s 10475.950us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 98.995us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 58.189us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 141.037us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 141.037us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 119.699us 1 1 100.00
aes_csr_rw 2.000s 133.549us 1 1 100.00
aes_csr_aliasing 2.000s 76.135us 1 1 100.00
aes_same_csr_outstanding 2.000s 93.285us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 119.699us 1 1 100.00
aes_csr_rw 2.000s 133.549us 1 1 100.00
aes_csr_aliasing 2.000s 76.135us 1 1 100.00
aes_same_csr_outstanding 2.000s 93.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 461.536us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 104.349us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1189.382us 1 1 100.00
aes_tl_intg_err 5.000s 3095.279us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 5.000s 3095.279us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 152.926us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
aes_core_fi 2.000s 130.609us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 98.995us 1 1 100.00
aes_config_error 3.000s 298.605us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_core_fi 2.000s 130.609us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 92.865us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 72.654us 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 112.240us 1 1 100.00
aes_sideload 2.000s 66.280us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.654us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.654us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 72.654us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 72.654us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 72.654us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 112.240us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 30.000s 10069.479us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 30.000s 10069.479us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 30.000s 10069.479us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 30.000s 10069.479us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 17.000s 10034.655us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_ctr_fi 2.000s 92.185us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 30.000s 10069.479us 0 1 0.00
aes_ghash_fi 3.000s 103.498us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 30.000s 10069.479us 0 1 0.00
aes_control_fi 2.000s 46.217us 1 1 100.00
aes_cipher_fi 22.000s 10016.481us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 144.190us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 84527915171285026363686398745650391424176024602167436237208718309068615515810 472
UVM_INFO @ 10034654595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 4315753227294794265690308004651883986512037087547651450739220114345006156428 26624
UVM_INFO @ 10475949678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 15338363132730023950765294742672237056383168191224738902025303314004715407148 2293
UVM_INFO @ 10069479289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 23579703491884136847119658760994331892096507027820144527711179137386740318733 157
UVM_INFO @ 10016481441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG
aes_stress_all_with_rand_reset 7727777890341918620765234553444366212213937812713415626591934758369580463974 364
UVM_INFO @ 144189992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---