Simulation Results: aes/unmasked

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.00 %
  • code
  • 91.21 %
  • assert
  • 97.75 %
  • func
  • 66.04 %
  • block
  • 91.50 %
  • line
  • 93.62 %
  • branch
  • 84.57 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 56.102us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 61.704us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 304.095us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 59.595us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 444.019us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 90.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 119.363us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 59.595us 1 1 100.00
aes_csr_aliasing 2.000s 90.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 61.704us 1 1 100.00
aes_config_error 2.000s 76.775us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 61.704us 1 1 100.00
aes_config_error 2.000s 76.775us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_b2b 7.000s 496.599us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 61.704us 1 1 100.00
aes_config_error 2.000s 76.775us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 66.603us 1 1 100.00
aes_config_error 2.000s 76.775us 1 1 100.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 1.000s 60.276us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 115.229us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 3.000s 898.418us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_sideload 3.000s 343.755us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 105.428us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 24.000s 10535.071us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 107.743us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 87.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 442.502us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 442.502us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 304.095us 1 1 100.00
aes_csr_rw 2.000s 59.595us 1 1 100.00
aes_csr_aliasing 2.000s 90.883us 1 1 100.00
aes_same_csr_outstanding 2.000s 71.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 304.095us 1 1 100.00
aes_csr_rw 2.000s 59.595us 1 1 100.00
aes_csr_aliasing 2.000s 90.883us 1 1 100.00
aes_same_csr_outstanding 2.000s 71.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 208.404us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 541.537us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 2646.066us 1 1 100.00
aes_tl_intg_err 2.000s 176.432us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 176.432us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 61.704us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
aes_core_fi 2.000s 79.322us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 107.743us 1 1 100.00
aes_config_error 2.000s 76.775us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_core_fi 2.000s 79.322us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 86.972us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 93.737us 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 81.113us 1 1 100.00
aes_sideload 3.000s 343.755us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 93.737us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 93.737us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 93.737us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 93.737us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 93.737us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 81.113us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 12.000s 10046.972us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 12.000s 10046.972us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 12.000s 10046.972us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 12.000s 10046.972us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 10.000s 10015.459us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_ctr_fi 2.000s 55.397us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 12.000s 10046.972us 0 1 0.00
aes_ghash_fi 2.000s 59.520us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 12.000s 10046.972us 0 1 0.00
aes_control_fi 2.000s 52.598us 1 1 100.00
aes_cipher_fi 3.000s 84.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 1068.372us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 93773276347326081821946247228534241788985834876501099264045037645707180343387 363
UVM_INFO @ 10015459247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 1856086842440506082614542948750892536286409735695758869308478854847503627580 76636
UVM_INFO @ 10535070975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 95208385487607915483376787570186105805260674670880138638408539207039702051436 1006
UVM_INFO @ 10046971573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 78158246684173685079168895272107175049582231184470630666814163775726774914058 1262
UVM_INFO @ 1068371529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---