Simulation Results: alert_handler

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.24 %
  • code
  • 90.04 %
  • assert
  • 96.40 %
  • func
  • 75.28 %
  • line
  • 99.59 %
  • branch
  • 98.44 %
  • cond
  • 91.95 %
  • toggle
  • 92.46 %
  • FSM
  • 67.74 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.170s 339.018us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.810s 594.241us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 269.290s 7974.736us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 181.710s 46577.103us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.340s 272.870us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.810s 594.241us 1 1 100.00
alert_handler_csr_aliasing 181.710s 46577.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 11.540s 1086.349us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 9.780s 187.806us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1402.230s 63283.758us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 6.230s 76.570us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 21.190s 509.628us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 14.130s 1152.536us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 187.100s 6628.897us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 724.250s 26191.454us 1 1 100.00
alert_handler_lpg_stub_clk 995.420s 10085.053us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 349.860s 9285.846us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 11.930s 1145.878us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.630s 18.320us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.400s 9.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.860s 62.776us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.860s 62.776us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.170s 339.018us 1 1 100.00
alert_handler_csr_rw 3.810s 594.241us 1 1 100.00
alert_handler_csr_aliasing 181.710s 46577.103us 1 1 100.00
alert_handler_same_csr_outstanding 26.140s 2738.150us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.170s 339.018us 1 1 100.00
alert_handler_csr_rw 3.810s 594.241us 1 1 100.00
alert_handler_csr_aliasing 181.710s 46577.103us 1 1 100.00
alert_handler_same_csr_outstanding 26.140s 2738.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 238.040s 4725.509us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 238.040s 4725.509us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 238.040s 4725.509us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 238.040s 4725.509us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 588.730s 5961.181us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
alert_handler_tl_intg_err 2.400s 33.473us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.400s 33.473us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 238.040s 4725.509us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 25.080s 375.205us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.230s 76.570us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 724.250s 26191.454us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.230s 76.570us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1402.230s 63283.758us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1402.230s 63283.758us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 16.390s 983.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 118.340s 4824.372us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 95242525215734575947915567809669193090791945285087389027654639534080555384123 120
UVM_INFO @ 6628896628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 33163890546122197021895071053779658915370224402411096790512456505134812257710 149
UVM_INFO @ 4824372401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---