Simulation Results: chip

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 67.38 %
  • code
  • 63.44 %
  • assert
  • 76.47 %
  • func
  • 62.22 %
  • line
  • 67.22 %
  • branch
  • 73.09 %
  • cond
  • 62.45 %
  • toggle
  • 57.31 %
  • FSM
  • 57.14 %
Validation stages
V1
27.27%
V2
30.65%
V2S
50.00%
V3
0.00%
unmapped
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_uart_tx_rx 0 1 0.00
chip_sw_uart_tx_rx 12.575s 0.000us 0 1 0.00
chip_sw_uart_rx_overflow 0 1 0.00
chip_sw_uart_tx_rx 12.575s 0.000us 0 1 0.00
chip_sw_uart_rand_baudrate 0 1 0.00
chip_sw_uart_rand_baudrate 38.662s 0.000us 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 0 1 0.00
chip_sw_uart_tx_rx_alt_clk_freq 39.354s 0.000us 0 1 0.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 362.210s 303.387us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 362.210s 303.387us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 362.210s 303.387us 1 1 100.00
chip_sw_example_tests 1 4 25.00
chip_sw_example_rom 31.100s 10.160us 0 1 0.00
chip_sw_example_manufacturer 21.204s 0.000us 0 1 0.00
chip_sw_example_concurrency 193.760s 169.964us 1 1 100.00
chip_sw_uart_smoketest_signed 15.652s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
chip_csr_bit_bash 9.010s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 9.120s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 1 0.00
chip_csr_aliasing 9.120s 0.000us 0 1 0.00
xbar_smoke 1 1 100.00
xbar_smoke 25.730s 63.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_spi_device_flash_mode 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 57.814s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 2285.650s 4232.315us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 295.370s 294.007us 0 1 0.00
chip_sw_spi_device_tpm 0 1 0.00
chip_sw_spi_device_tpm 16.667s 0.000us 0 1 0.00
chip_sw_spi_host_tx_rx 0 1 0.00
chip_sw_spi_host_tx_rx 21.108s 0.000us 0 1 0.00
chip_sw_i2c_host_tx_rx 0 1 0.00
chip_sw_i2c_host_tx_rx 14.838s 0.000us 0 1 0.00
chip_sw_i2c_device_tx_rx 0 1 0.00
chip_sw_i2c_device_tx_rx 20.934s 0.000us 0 1 0.00
chip_pin_mux 0 1 0.00
chip_padctrl_attributes 3.180s 0.000us 0 1 0.00
chip_padctrl_attributes 0 1 0.00
chip_padctrl_attributes 3.180s 0.000us 0 1 0.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 15.903s 0.000us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 18.672s 0.000us 0 1 0.00
chip_sw_data_integrity 0 1 0.00
chip_sw_data_integrity_escalation 9.359s 0.000us 0 1 0.00
chip_sw_instruction_integrity 0 1 0.00
chip_sw_data_integrity_escalation 9.359s 0.000us 0 1 0.00
chip_jtag_csr_rw 0 1 0.00
chip_jtag_csr_rw 93.760s 117.000us 0 1 0.00
chip_jtag_mem_access 0 1 0.00
chip_jtag_mem_access 100.280s 117.029us 0 1 0.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 312.060s 310.289us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 9.068s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 8.655s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 77.480s 130.424us 0 1 0.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 255.360s 268.394us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 0 1 0.00
chip_sw_aon_timer_irq 456.470s 556.986us 0 1 0.00
chip_sw_aon_timer_wdog_bark_irq 0 1 0.00
chip_sw_aon_timer_irq 456.470s 556.986us 0 1 0.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 415.860s 389.969us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 232.720s 183.973us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 232.720s 183.973us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 360.730s 2309.733us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 194.650s 164.638us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 314.110s 245.266us 1 1 100.00
chip_sw_aes_idle 205.150s 165.617us 1 1 100.00
chip_sw_hmac_enc_idle 197.770s 181.029us 1 1 100.00
chip_sw_kmac_idle 190.560s 164.665us 1 1 100.00
chip_sw_clkmgr_off_trans 0 4 0.00
chip_sw_clkmgr_off_aes_trans 189.100s 185.248us 0 1 0.00
chip_sw_clkmgr_off_hmac_trans 195.350s 185.296us 0 1 0.00
chip_sw_clkmgr_off_kmac_trans 200.920s 185.264us 0 1 0.00
chip_sw_clkmgr_off_otbn_trans 198.610s 185.232us 0 1 0.00
chip_sw_clkmgr_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.670s 10.360us 0 1 0.00
chip_sw_aes_enc_jitter_en 35.870s 10.360us 0 1 0.00
chip_sw_hmac_enc_jitter_en 35.990s 10.380us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 35.470s 10.120us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 37.070s 10.300us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.950s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 196.380s 161.083us 1 1 100.00
chip_sw_clkmgr_extended_range 1 8 12.50
chip_sw_clkmgr_jitter_reduced_freq 411.820s 1960.022us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 34.600s 10.240us 0 1 0.00
chip_sw_aes_enc_jitter_en_reduced_freq 37.240s 10.200us 0 1 0.00
chip_sw_hmac_enc_jitter_en_reduced_freq 36.410s 10.260us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 36.290s 10.400us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 36.820s 10.220us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 35.380s 10.300us 0 1 0.00
chip_sw_csrng_edn_concurrency_reduced_freq 34.670s 10.220us 0 1 0.00
chip_sw_clkmgr_deep_sleep_frequency 0 1 0.00
chip_sw_ast_clk_outputs 49.146s 0.000us 0 1 0.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 9.556s 0.000us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 11.733s 0.000us 0 1 0.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 112.020s 118.408us 0 1 0.00
chip_sw_pwrmgr_sleep_all_reset_reqs 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 232.720s 183.973us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 0 1 0.00
chip_sw_pwrmgr_wdog_reset 9.033s 0.000us 0 1 0.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 112.020s 118.408us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 9.525s 0.000us 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 24.031s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 11.341s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 8.959s 0.000us 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 0 1 0.00
chip_sw_pwrmgr_sleep_disabled 9.608s 0.000us 0 1 0.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 312.060s 310.289us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 385.230s 414.496us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 306.690s 305.518us 1 1 100.00
chip_sw_rstmgr_alert_info 0 1 0.00
chip_sw_rstmgr_alert_info 376.610s 336.300us 0 1 0.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 194.520s 163.413us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 17.917s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 0 1 0.00
chip_sw_alert_handler_escalation 38.253s 0.000us 0 1 0.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 31.352s 0.000us 0 1 0.00
chip_sw_alert_handler_crashdump 0 1 0.00
chip_sw_rstmgr_alert_info 376.610s 336.300us 0 1 0.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 277.870s 280.435us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 24.415s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 30.785s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 0 1 0.00
chip_sw_alert_handler_lpg_clkoff 66.321s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 0 1 0.00
chip_sw_alert_handler_lpg_reset_toggle 61.029s 0.000us 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 1 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11.973s 0.000us 0 1 0.00
chip_sw_lc_ctrl_alert_handler_escalation 0 1 0.00
chip_sw_alert_handler_escalation 38.253s 0.000us 0 1 0.00
chip_sw_lc_ctrl_jtag_access 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 8.654s 0.000us 0 1 0.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_lc_ctrl_key_div 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_prod 324.500s 305.519us 0 1 0.00
chip_sw_lc_ctrl_broadcast 0 10 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 11.487s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 14.697s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 9.996s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 10.668s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 317.120s 305.595us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 177.540s 157.672us 0 1 0.00
chip_sw_sram_ctrl_execution_main 10.928s 0.000us 0 1 0.00
chip_prim_tl_access 82.110s 127.096us 0 1 0.00
chip_rv_dm_lc_disabled 77.480s 130.424us 0 1 0.00
chip_sw_aes_enc 1 2 50.00
chip_sw_aes_enc 227.070s 176.101us 1 1 100.00
chip_sw_aes_enc_jitter_en 35.870s 10.360us 0 1 0.00
chip_sw_aes_gcm 1 2 50.00
chip_sw_aes_enc 227.070s 176.101us 1 1 100.00
chip_sw_aes_enc_jitter_en 35.870s 10.360us 0 1 0.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 193.830s 164.996us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 205.150s 165.617us 1 1 100.00
chip_sw_hmac_enc 1 2 50.00
chip_sw_hmac_enc 206.180s 175.742us 1 1 100.00
chip_sw_hmac_enc_jitter_en 35.990s 10.380us 0 1 0.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 197.770s 181.029us 1 1 100.00
chip_sw_kmac_enc 2 3 66.67
chip_sw_kmac_mode_cshake 186.100s 168.441us 1 1 100.00
chip_sw_kmac_mode_kmac 245.480s 191.666us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 37.070s 10.300us 0 1 0.00
chip_sw_kmac_app_keymgr 0 1 0.00
chip_sw_keymgr_dpe_key_derivation 317.120s 305.595us 0 1 0.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_kmac_app_rom 0 1 0.00
chip_sw_kmac_app_rom 48.011s 0.000us 0 1 0.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 279.880s 208.986us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 190.560s 164.665us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1616.170s 2224.494us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1616.170s 2224.494us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 11.522s 0.000us 0 1 0.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 228.710s 176.443us 1 1 100.00
chip_sw_edn_entropy_reqs 1 1 100.00
chip_sw_csrng_edn_concurrency 2209.950s 1727.533us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 0 2 0.00
chip_sw_keymgr_dpe_key_derivation 317.120s 305.595us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 35.470s 10.120us 0 1 0.00
chip_sw_otbn_op 1 2 50.00
chip_sw_otbn_ecdsa_op_irq 2740.710s 1497.224us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.670s 10.360us 0 1 0.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 314.110s 245.266us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 314.110s 245.266us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 314.110s 245.266us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 379.840s 279.309us 1 1 100.00
chip_sw_rom_access 0 1 0.00
chip_sw_rom_ctrl_integrity_check 177.540s 157.672us 0 1 0.00
chip_sw_rom_ctrl_integrity_check 0 1 0.00
chip_sw_rom_ctrl_integrity_check 177.540s 157.672us 0 1 0.00
chip_sw_sram_scrambled_access 1 2 50.00
chip_sw_sram_ctrl_scrambled_access 411.650s 352.669us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.950s 0.000us 0 1 0.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 10.928s 0.000us 0 1 0.00
chip_sw_sram_lc_escalation 0 2 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_data_integrity_escalation 9.359s 0.000us 0 1 0.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_otp_ctrl_keys 3 4 75.00
chip_sw_otbn_mem_scramble 379.840s 279.309us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 317.120s 305.595us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 411.650s 352.669us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 198.400s 179.805us 1 1 100.00
chip_sw_otp_ctrl_entropy 3 4 75.00
chip_sw_otbn_mem_scramble 379.840s 279.309us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 317.120s 305.595us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access 411.650s 352.669us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 198.400s 179.805us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program_error 0 1 0.00
chip_sw_lc_ctrl_program_error 9.120s 0.000us 0 1 0.00
chip_sw_otp_ctrl_hw_cfg 0 1 0.00
chip_sw_lc_ctrl_otp_hw_cfg 8.654s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals 0 6 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 11.487s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_dev 14.697s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_prod 9.996s 0.000us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_rma 10.668s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 11.921s 0.000us 0 1 0.00
chip_prim_tl_access 82.110s 127.096us 0 1 0.00
chip_sw_otp_prim_tl_access 0 1 0.00
chip_prim_tl_access 82.110s 127.096us 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 0 1 0.00
chip_sw_otp_ctrl_nvm_cnt 8.636s 0.000us 0 1 0.00
chip_sw_otp_ctrl_sw_parts 0 1 0.00
chip_sw_otp_ctrl_sw_parts 9.286s 0.000us 0 1 0.00
chip_sw_ast_clk_outputs 0 1 0.00
chip_sw_ast_clk_outputs 49.146s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 1 7 14.29
chip_sw_otbn_ecdsa_op_irq_jitter_en 34.670s 10.360us 0 1 0.00
chip_sw_aes_enc_jitter_en 35.870s 10.360us 0 1 0.00
chip_sw_hmac_enc_jitter_en 35.990s 10.380us 0 1 0.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 35.470s 10.120us 0 1 0.00
chip_sw_kmac_mode_kmac_jitter_en 37.070s 10.300us 0 1 0.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 8.950s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter 196.380s 161.083us 1 1 100.00
chip_sw_soc_proxy_external_reset_requests 0 1 0.00
chip_sw_soc_proxy_smoketest 174.730s 156.944us 0 1 0.00
chip_sw_soc_proxy_external_irqs 0 1 0.00
chip_sw_soc_proxy_smoketest 174.730s 156.944us 0 1 0.00
chip_sw_soc_proxy_external_wakeup_requests 0 1 0.00
chip_sw_soc_proxy_external_wakeup 179.680s 157.913us 0 1 0.00
chip_sw_soc_proxy_gpios 1 1 100.00
chip_sw_soc_proxy_gpios 178.720s 180.267us 1 1 100.00
chip_sw_nmi_irq 0 1 0.00
chip_sw_rv_core_ibex_nmi_irq 391.830s 272.201us 0 1 0.00
chip_sw_rv_core_ibex_rnd 0 1 0.00
chip_sw_rv_core_ibex_rnd 223.790s 184.673us 0 1 0.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 237.610s 184.291us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 198.400s 179.805us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 385.230s 414.496us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 385.230s 414.496us 0 1 0.00
chip_sw_smoketest 14 14 100.00
chip_sw_aes_smoketest 209.220s 176.125us 1 1 100.00
chip_sw_aon_timer_smoketest 210.450s 182.444us 1 1 100.00
chip_sw_clkmgr_smoketest 182.800s 162.227us 1 1 100.00
chip_sw_csrng_smoketest 180.780s 164.344us 1 1 100.00
chip_sw_gpio_smoketest 221.320s 193.174us 1 1 100.00
chip_sw_hmac_smoketest 242.510s 201.569us 1 1 100.00
chip_sw_kmac_smoketest 230.830s 190.526us 1 1 100.00
chip_sw_otbn_smoketest 266.590s 205.408us 1 1 100.00
chip_sw_otp_ctrl_smoketest 197.030s 166.374us 1 1 100.00
chip_sw_rv_plic_smoketest 173.310s 164.227us 1 1 100.00
chip_sw_rv_timer_smoketest 245.450s 268.377us 1 1 100.00
chip_sw_rstmgr_smoketest 190.800s 160.774us 1 1 100.00
chip_sw_sram_ctrl_smoketest 169.770s 164.811us 1 1 100.00
chip_sw_uart_smoketest 193.320s 174.857us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 9.406s 0.000us 0 1 0.00
chip_sw_signed 0 1 0.00
chip_sw_uart_smoketest_signed 15.652s 0.000us 0 1 0.00
chip_sw_boot 0 1 0.00
chip_sw_uart_tx_rx_bootstrap 57.814s 0.000us 0 1 0.00
chip_sw_secure_boot 0 1 0.00
base_rom_e2e_smoke 7.998s 0.000us 0 1 0.00
chip_lc_scrap 0 4 0.00
chip_sw_lc_ctrl_rma_to_scrap 193.690s 173.592us 0 1 0.00
chip_sw_lc_ctrl_raw_to_scrap 155.130s 169.672us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 165.520s 173.240us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 169.100s 164.136us 0 1 0.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 9.202s 0.000us 0 1 0.00
chip_rv_dm_lc_disabled 77.480s 130.424us 0 1 0.00
chip_sw_lc_walkthrough 0 5 0.00
chip_sw_lc_walkthrough_dev 12.228s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 26.229s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 9.603s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_rma 19.267s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 9.202s 0.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 284.080s 399.832us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 475.010s 599.880us 0 1 0.00
rom_volatile_raw_unlock 18.477s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 23.877s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 13.058s 0.000us 0 1 0.00
chip_sw_inject_scramble_seed 0 1 0.00
chip_sw_inject_scramble_seed 74.002s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 118.560s 118.026us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 118.560s 118.026us 0 1 0.00
tl_d_outstanding_access 0 2 0.00
chip_csr_aliasing 9.120s 0.000us 0 1 0.00
chip_same_csr_outstanding 9.060s 0.000us 0 1 0.00
tl_d_partial_access 0 2 0.00
chip_csr_aliasing 9.120s 0.000us 0 1 0.00
chip_same_csr_outstanding 9.060s 0.000us 0 1 0.00
xbar_base_random_sequence 1 1 100.00
xbar_random 198.930s 484.331us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 13.620s 11.716us 1 1 100.00
xbar_smoke_large_delays 289.660s 2343.878us 1 1 100.00
xbar_smoke_slow_rsp 353.960s 1933.696us 1 1 100.00
xbar_random_zero_delays 71.160s 54.144us 1 1 100.00
xbar_random_large_delays 222.520s 1758.652us 1 1 100.00
xbar_random_slow_rsp 1820.050s 9836.505us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 63.300s 39.065us 1 1 100.00
xbar_error_and_unmapped_addr 31.040s 53.197us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 46.130s 45.291us 1 1 100.00
xbar_error_and_unmapped_addr 31.040s 53.197us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 114.160s 253.576us 1 1 100.00
xbar_access_same_device_slow_rsp 2570.060s 14745.753us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 41.920s 82.824us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 325.290s 670.860us 1 1 100.00
xbar_stress_all_with_error 167.620s 138.932us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 816.440s 796.854us 1 1 100.00
xbar_stress_all_with_reset_error 1236.440s 2163.797us 1 1 100.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 9.650s 0.000us 0 1 0.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 10.612s 0.000us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 12.679s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 39.439s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 23.354s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 11.631s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 22.723s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 10.436s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 107.674s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 13.224s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 9.007s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 13.583s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 8.849s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 110.737s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 49.840s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 11.816s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.157s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 11.088s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 136.217s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 26.819s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 22.276s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.183s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 22.022s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 104.216s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.626s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 13.679s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 12.188s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 9.693s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 99.202s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 12.695s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 9.075s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 9.946s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 9.932s 0.000us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 115.154s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 8.700s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 10.658s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 15.179s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 12.159s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 12.063s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 12.928s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 14.100s 0.000us 0 1 0.00
rom_e2e_static_critical 0 1 0.00
rom_e2e_static_critical 8.723s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 228.130s 195.054us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 159.290s 136.405us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 15.314s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 11.326s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 16.139s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 9.888s 0.000us 0 1 0.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 882.310s 950.624us 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 0 1 0.00
chip_sw_otp_ctrl_vendor_test_csr_access 12.166s 0.000us 0 1 0.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 203.870s 180.628us 0 1 0.00
chip_sw_coremark 0 1 0.00
chip_sw_coremark 15.709s 0.000us 0 1 0.00
chip_sw_power_max_load 0 1 0.00
chip_sw_power_virus 77.090s 0.000us 0 1 0.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 15.314s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 11.326s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 16.139s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 10.238s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 9.339s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 9.923s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 107.583s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 20 40.00
chip_sw_rstmgr_rst_cnsty_escalation 915.340s 950.612us 0 1 0.00
chip_sw_aes_gcm 253.890s 207.219us 1 1 100.00
chip_sw_entropy_src_kat_test 189.240s 163.516us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 171.620s 161.180us 1 1 100.00
chip_plic_all_irqs_0 486.870s 356.428us 1 1 100.00
chip_plic_all_irqs_10 453.710s 321.281us 1 1 100.00
chip_sw_dma_inline_hashing 252.340s 209.240us 1 1 100.00
chip_sw_dma_abort 280.960s 212.061us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 96.051s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 91.999s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_otbn 9.189s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_dev_sw 8.326s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_otbn 8.002s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_sw 8.072s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_otbn 8.055s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_prod_end_sw 7.830s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_otbn 8.063s 0.000us 0 1 0.00
rom_e2e_sigverify_mod_exp_rma_sw 7.958s 0.000us 0 1 0.00
chip_sw_entropy_src_smoketest 257.400s 198.293us 1 1 100.00
chip_sw_mbx_smoketest 348.240s 319.627us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
chip_csr_bit_bash 32580527473276662451370582094914592371633470720469463263479218082125930445867 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_aliasing 77104934614518966851342344826959854423429849014003534216800315706058221171585 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_same_csr_outstanding 68513748821794764276723961081742163091864660156007364335998629937481710182699 136
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode
chip_sw_example_rom 17427535854188610174572222848100099588031738134641789704657555635652593330908 284
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_example_manufacturer 21876105934575922950651403903039021976381444525250506494591161421879924106943 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 9.673s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_data_integrity_escalation 25410423038719897689011095333729251995363098198700167269357198032091352455098 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.262s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_wake 10953739121778095222914556828260218702385120754737275126778991018066377386960 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.153s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sleep_pin_retention 619342061719427284141985645516509921843325544178030855894007666231780237303 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.231s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx 104857379182389385283101088690508579793057480866984104736693486011944398887768 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.353s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_bootstrap 62109058929098937711771975424012768026903020732912790348122405886257145634851 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 8.778s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_inject_scramble_seed 72693394857233696404773357835831324352264912238402636353245725404342624636980 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 63.435s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_exit_test_unlocked_bootstrap 1409402794531078890457476416446270112621785964047763266231486789589843957080 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.632s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_rand_baudrate 110476947370235038780346574859913222674663552173779868550673931807834915007581 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.041s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_tx_rx_alt_clk_freq 64308460326233189940097597151251595227735799436464211343359230489070729217118 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:uart_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.606s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_host_tx_rx 69449355436251654939728696040911043405493058795709159985208497975279562568562 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 2.095s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_i2c_device_tx_rx 106800683055096178313177297417319077535461734916750497929036113850478871138942 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.254s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_device_tpm 27582685231176991266013724760314393613832077561940344924442048879382946404199 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.745s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_spi_host_tx_rx 42289196333441315042112333188591890314501219201511881043548734347125526933278 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.129s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_otp_hw_cfg 115315736471814096599453347304846011973688333626192559009050532725329192458173 None
---- STDERR ----
Another command (pid=1237352) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_test_unlocked0 76787239097956450846054993100462816503211553976551811520453128629173119676408 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.412s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_dev 70291928969623599956292043924422846871989904527967395369386140872059833825698 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.586s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_prod 26931834092471815398494172815844389022690921890881956308271050060169460267029 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.286s, Critical Path: 0.01s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_lc_signals_rma 22956919087251198438954113172117860431214846769378854011208897375381428366269 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.304s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_vendor_test_csr_access 66220385993705397680464550046543303586655828964905666320970528790957495923506 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.736s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_nvm_cnt 52108385822982427671412602657471029001497523599280753827522119438266255565571 None
---- STDERR ----
Another command (pid=528116) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_otp_ctrl_sw_parts 81771923895344412839866948602868042736740838948896245863257554456345231650004 None
---- STDERR ----
Another command (pid=514319) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=533088) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_transition 7850722910375049159062779310616315611077617080111296639751155132285457976052 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.823s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_dev 10655995248748213851317996439807542006268929118352201774389101236290021038048 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.128s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prod 115681005649302267652839277349044997749868551523159162162380796874426244443689 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.753s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_prodend 28143516749120311103742380540246796528180002903693978224266382803296640572397 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.255s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_rma 25263123287458584205313388353728966150465126541489933301433935940658918206284 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.763s, Critical Path: 0.10s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_walkthrough_testunlocks 108700068487093454262817825221685544852812569377831459689617533563170920399453 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.288s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_main_power_glitch_reset 8398432057784579622919681219463674488226696957878390376001323772224580620588 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.285s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_power_glitch_reset 32918435131366021556057606397605456497110023393509871808215270115868807989646 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.264s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 696990141905216274469408530245965242739501771519606783004893250716584077529 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.407s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_random_sleep_power_glitch_reset 55130153652107315159906404850075636366365411523093429265707165661582680423933 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.745s, Critical Path: 0.08s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_disabled 115185974360790405057239203998569148884713240660524332817803360511656670840423 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.260s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_wdog_reset 60689956601942257523262869911382879299892449190696210108965386784640745377952 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.235s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_test 48825748527220923950070266527817210453891544421839996678342254051432282186476 None
Another command (pid=709118) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- sw/device/tests/autogen/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_escalation 113586615763688668248442830525904882166800902386214334136629330821814186217674 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.243s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14639256135018914841473741761282237204875349413491591279677516812832547085474 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.260s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_alerts 27237134019173194934907568369302712595799117621327799040827040962399415024090 None
Another command (pid=429322) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=492373) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=419821) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_sleep_mode_pings 33798184391881732474017741958950235010693023956788885150844878622565428436221 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.717s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_clkoff 41671881041917785199408590755073015062950783574460424697008297681681991691616 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.910s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_lpg_reset_toggle 25768797621129920276094565951063769691382160266886728176326138245817310482603 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 4.467s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_alert_handler_entropy 15145930758133038886069796323925595507912934470688133340687348876690762677116 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.222s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_csrng_fuse_en_sw_app_read_test 101707251215699739645639258769251841322259358185263289172311333519225919458753 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.785s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_kmac_app_rom 25547451193941700788900702442096792964983422363102734931139859613905330717196 None
---- STDERR ----
Another command (pid=1230068) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=1228231) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=1234718) is running. Waiting for it to complete on the server (server_pid=272465)...
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_scrambled_access_jitter_en 89503419953433828251772778723532355750166852194230113619420927797599634254154 None
---- STDERR ----
Another command (pid=1414973) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=1419046) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_sram_ctrl_execution_main 64912169075877666828226671166426172760874905580047222416215529120028912318554 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.949s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_coremark 5421714758439627976293952172054930127758053104149514101653984844941888884350 None
Another command (pid=536259) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.
- third_party/coremark/top_darjeeling
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_reset_frequency 94122099132923078889026607488214557159969410200730903253842247411156520206359 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.844s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_clkmgr_sleep_frequency 16504264276677911030016724483766801314855122074666195899164151593748905522978 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.301s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_ast_clk_outputs 11492890899668224265685274145027145889714193889336406486541984003075985460021 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:ast_clk_outs_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 3.221s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_lc_ctrl_program_error 18727377036398883411234850413310735843926622667468976601149565192070002731146 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.500s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 88490587022831670042376398943767430030913257040904645765313510373453335456929 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_wakeup 71883705300530713836363336072222989493101298225905124124222560363601324315583 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_rv_dm_access_after_escalation_reset 3791443848584393391434053193286237143963960620888523146660437308581433251525 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.232s, Critical Path: 0.02s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_power_virus 96433681295954658949366633652240962095837596395019111797137052248793996639077 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/tests:power_virus_systemtest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.176s, Critical Path: 0.04s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
base_rom_e2e_smoke 59305308465576054935271957529331297890497388984596200651967627556178887062505 None
_deploy_software_collateral(args)
~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_smoke 83528970381882818287488034317096189565416768065125430977670095869702930216751 None
---- STDERR ----
Another command (pid=1438388) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_exception_c 107256764504368093419319160776820144230842719008501641558043112058793584617297 None
---- STDERR ----
Another command (pid=604951) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_shutdown_output 72719491273824705906701182934463543852976166583890811128933484793307685704515 None
Another command (pid=607223) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=602690) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=610400) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 12789950173577284416810036129593727112851264120290200879349202131826980070774 None
Another command (pid=327527) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=387064) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=400942) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 6559429216491989940613791318010388664761831435652172237207058838969791904773 None
Another command (pid=577025) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=547648) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=554590) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 28919189677185873164148574116567374156744140756785046253198661162432292563508 None
Another command (pid=553575) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=557181) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=547435) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 115543198137462650064334835264245723341961806435135431397146440679783722601153 None
Another command (pid=577482) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=577025) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=547648) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 31115272424276753444086919384320534392834006653645348802385157878207950690539 None
Another command (pid=562621) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=567593) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=570097) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 71110449920939507367919354862506684867043106677138951125014559892179698653190 None
Another command (pid=490545) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=501222) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=492874) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 52934384959498991499369739016872891307382082437168455058337549287305033430191 None
Another command (pid=547435) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=544097) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=548725) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 83453686995681889597789126473335151111110705766156160965709246906937903722919 None
---- STDERR ----
Another command (pid=547362) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 12312232875236168605392226054735244611764040092522214256239143710961682734383 None
Another command (pid=553674) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=548725) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=548563) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 90754785525292027980253125708818713858798894316603357578429365581748318233686 None
---- STDERR ----
Another command (pid=552207) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 13294088052816653600377014205584558221204812271623694481282778611323335639913 None
Another command (pid=403853) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=429322) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=331433) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 96769681532708319548558243384328104959118226504826052873305274949729191031381 None
Another command (pid=619908) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=638042) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=583615) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 92783326218344055536537333271000892931698340197026364948813536007572453915676 None
Another command (pid=523592) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=552724) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=552966) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 93290977121227608744582149932180721346730562335168558423688636154872314933815 None
Another command (pid=562621) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=567593) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=570097) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 53694675710396443674261866515730192051510212257970628966975339965159018285762 None
---- STDERR ----
Another command (pid=514377) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 41378728868575913628436607253121382424830233181120136873789964646870751361972 None
---- STDERR ----
Another command (pid=490545) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_dev 4248847735398843541517914373831294574548422744041782764015868421701323398872 None
Another command (pid=656497) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=646216) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=659479) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod 95861948736129466644111141625438569138925205476670148678077335487999595602477 None
---- STDERR ----
Another command (pid=652288) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 33048403706358674748856480708049839737906244862371838064311963495476949520802 None
---- STDERR ----
Another command (pid=641900) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_bad_rma 77022578897997546957495357942552372896386020253961609414853653970667736485265 None
Another command (pid=654020) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=659479) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=659773) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 106250912207250897069609998488808196751098378300678574914483379979620166772271 None
Another command (pid=498049) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=476731) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=509324) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_dev 106916588690630334050871660208026336723417839688958680049185508328690392395309 None
Another command (pid=621807) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=639214) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=625571) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod 113413482403540394513306209759628858910444616344105362438179682794804548670028 None
---- STDERR ----
Another command (pid=626517) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=635816) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 76728655165579734578887787207528861260529726749006917321270193048291579302402 None
---- STDERR ----
Another command (pid=626188) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_bad_b_nothing_rma 44860071865702606656765712955925034707978515346024042047090050602767479907427 None
Another command (pid=636285) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=636113) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=622385) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 39202920326619530826649297781104696454380125487745220953689690328899141207375 None
Another command (pid=376959) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=365505) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=498049) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_dev 111442995239230197363764242505587523084986633312702527254395875546647058013346 None
Another command (pid=589421) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=635309) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=619908) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod 50717977373078765107692534511028170007349607482693708019283155981725384858626 None
---- STDERR ----
Another command (pid=632727) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 54248594088261876283848044674436770849576186892977619891805354621162683825150 None
---- STDERR ----
Another command (pid=611642) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=652288) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_always_a_nothing_b_bad_rma 53536606866360157198889322518099355879872742080315076029385033392358389321496 None
---- STDERR ----
Another command (pid=659892) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=661132) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 80640220528332542015582506439822910247403614579508318428496509857773576842327 None
Another command (pid=403853) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=420631) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=331433) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 37030044755673258440795274788953566676490141687529736903635685066064966034876 None
---- STDERR ----
Another command (pid=527226) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 73985853684292049422981691499310366582069571729989614223561805235766020585740 None
Another command (pid=536259) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=537540) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=534026) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 35602663374213856051566150122640792269253384729531709911402150571305153925876 None
Another command (pid=548227) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=557181) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=547435) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 27908627133799642986594879953124390612283759938139888787069727763772980589233 None
Another command (pid=523592) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=552724) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=552966) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_test_unlocked0 86937207692161101948818426623244039644842669965904934754888552208181047379454 None
Another command (pid=590833) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=583912) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=600071) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_dev 6963222989342999348216397459213236311842198439815941291744811366003721588157 None
Another command (pid=577482) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=577025) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=547648) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_debug_rma 82416188787540306743740333921566492763715132085655373538559269386440526403031 None
Another command (pid=590833) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=583912) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=600071) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_test_unlocked0 21951596554987026548821249628383126649718823930758127998647266619553433221206 None
Another command (pid=518927) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=514603) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=525585) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_dev 17997728185268603685504819181072989023435614988878678254282567915188918710814 None
---- STDERR ----
Another command (pid=521301) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=522017) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_jtag_inject_rma 33364339736139643242576919222112213739607562658148630731050587893953141406237 None
Another command (pid=522017) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=514603) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=520840) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_static_critical 72173766410788868906268386712731165493526934140827299572671888553061585608568 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_meas 30994661954429656364460233918578033438553852216424456602032423293622090126424 None
Another command (pid=585129) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=591982) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=579358) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_no_meas 21058375190223504576308604552701032499192908025023501567714963323581886514757 None
Another command (pid=594440) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=590833) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=600071) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_keymgr_init_rom_ext_invalid_meas 55515555318711668603900099278198125668262414143302020678359875158373949255601 None
Another command (pid=600071) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=519114) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=593332) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_otbn 70507396937921770873956184252341427389604460448739796086230692128886855389366 None
Another command (pid=501222) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=492874) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=369830) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_test_unlocked0_sw 110714407397883154247840519819540750998064916523031904924725224400204047076680 None
Another command (pid=420631) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=331433) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=351577) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_otbn 101467332709135961179487005115487224101834322480572075956335650525566561468781 None
Another command (pid=659773) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=660278) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=661132) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_dev_sw 30484896657898019732531329614687889388442989501829283999479428460652451836168 None
---- STDERR ----
Another command (pid=661132) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_otbn 100187059581490396535213703489236774565011401555046425532396652764039187205870 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_sw 115574449189279041432034860303849202706115470475883598675620462072078326148041 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_otbn 59738265348683847977820519844004482101059734376058602726857478883466341485950 None
---- STDERR ----
Another command (pid=661132) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_prod_end_sw 52238316879483752918081497514773417465504022537182771898272526465325352976863 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_otbn 86622412322412157527543772293599309550791602459464498309165853194486251957377 None
---- STDERR ----
Another command (pid=671927) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_sigverify_mod_exp_rma_sw 106256657468858545922625648433178980966979129457341196454133463279867231010302 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 28588810868839116459482210489099796403624677005175015959448452027956727110809 None
---- STDERR ----
Another command (pid=327527) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 20706100844370074801510882010875511774423170272033753961901008940937432595467 None
---- STDERR ----
Another command (pid=327527) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=397857) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 101488043345458841703194819046572161527136798382054619174754200245421137147624 None
Another command (pid=420162) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=498049) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=476731) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_uart_smoketest_signed 87767582014701543623829643383426156326734486334823199983397073106522737491943 None
Another command (pid=529092) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=534026) is running. Waiting for it to complete on the server (server_pid=272465)...
Another command (pid=530695) is running. Waiting for it to complete on the server (server_pid=272465)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_keymgr_functest 95582721308670661185767668137048499325169991261914929717468683474780618320667 None
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb) <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 0.278s, Critical Path: 0.03s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size
chip_sw_all_escalation_resets 60680410062116717199962844997726671782444470098311827689772840741336810117836 349
UVM_INFO @ 950.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 38218833171229596558699112051162619491973216461214253226266014089834992857308 348
UVM_INFO @ 950.612000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 36805520123958886593746270423262453819890668436811583934898371637682357235111 332
UVM_INFO @ 294.007000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 29569913460276851889066548521583276539770072968816597481718138153953203308182 328
UVM_ERROR @ 180.628000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 180.628000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_lc_ctrl_rma_to_scrap 103360547669510160581335504767433136657224561918439438904526780443235291065963 333
UVM_ERROR @ 173.592000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 173.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_raw_to_scrap 105179302117857149389682207087363212309080689454829270973776592779120757318111 322
UVM_ERROR @ 169.672000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 169.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_test_locked0_to_scrap 85850822565056973051007265030373561529846151111877549800666306378347332527734 322
UVM_ERROR @ 173.240000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 173.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_rand_to_scrap 109111233138855600206684102813573738015960061776882800529947260681532492158372 325
UVM_ERROR @ 164.136000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 164.136000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_volatile_raw_unlock 41400271338174327432775650162444833380817313375509208760752952374748449585625 325
UVM_ERROR @ 399.832000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 399.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 108283718868748742125582057009464232456312726985468059900201679368049907280387 328
UVM_ERROR @ 599.880000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 599.880000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 7522183685916883428780203109064826902950740004108367350149421347849503205507 316
UVM_ERROR @ 118.408000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 118.408000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rom_ctrl_integrity_check 67263214049341241412667721488787406815998396279714876165302967038424439017187 324
UVM_ERROR @ 157.672000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 157.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_prim_tl_access 21444624452156987040390058926322909978202604189234144460531041518490537003866 231
UVM_ERROR @ 127.096000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 127.096000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 59056027859813168342178242639357633401222482121901875361802817149901262679588 211
UVM_ERROR @ 130.424000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 130.424000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size
chip_sw_rstmgr_alert_info 4271939655906166532619141151080492509361339978675202106941862784657674223739 342
UVM_INFO @ 336.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!rstreqs[*]) && (reset_cause != HwReq))'
chip_sw_rstmgr_cpu_info 8892895790870285617960569172501072537897275579369709146200736201190307874600 346
UVM_ERROR @ 414.496000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 414.496000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_aes_trans 98573163638343009792553044443243044268489125142622265106876783962777226230682 323
UVM_ERROR @ 185.248000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_hmac_trans 38415257949913401939389642612539549652138004059361360176483295478588828331458 323
UVM_ERROR @ 185.296000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.296000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_kmac_trans 16022307052341526427993174949404618626412033689504658427798714232067246748487 323
UVM_ERROR @ 185.264000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.264000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_off_otbn_trans 40922866718922591017891546623330026364011626320281930337744859870273716923535 323
UVM_ERROR @ 185.232000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 185.232000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
chip_sw_soc_proxy_smoketest 71423323951735580741397905516633807888154763461543206459373061261158261628536 321
UVM_INFO @ 156.944000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *
chip_sw_soc_proxy_external_wakeup 81571892148015306365138263065752404055798865472122506723213219446571267354672 319
UVM_INFO @ 157.913000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec
chip_sw_aon_timer_irq 75204540576964820943169834746132923743703535892189869393944764762071812876574 320
UVM_INFO @ 556.986000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds
chip_sw_aon_timer_wdog_bite_reset 86148404647422486789561859649253935265268286268760805273276181898251844239908 321
UVM_INFO @ 183.973000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:267) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
chip_sw_otbn_ecdsa_op_irq_jitter_en 52884968490831677339244382664526651810547673773502455670972898157203310401186 312
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en 26124063453545305159463080968521373685393567834615218134306319056469507124529 312
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en 19123643533519629530729976884442590193026895690695428107675089948117875264662 312
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en 48983481164521164325645826583208306663526444943627464490936644741086532157367 312
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en 54089855569620621874997784553673050239269314076500680284114464514975364247754 312
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 111358472413019484071601681462443675185615269769956130544064702749668233835297 312
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aes_enc_jitter_en_reduced_freq 86448096274028781985729547438256675703719313640721789175788085600219320433392 312
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_enc_jitter_en_reduced_freq 14317387428140487281721375010844457027464801002217056219925378625365062036047 312
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 45564216760550698564297561599773044991911604087843520326765114106057851593988 312
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 85462307622595815839816409986263156458168974090791028109534777352380325222086 312
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 82507346352847333915517032635955606998401039486246320333131905500346258721500 312
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_edn_concurrency_reduced_freq 72536781455797185430776000693889817922386972590928208226601179735149589524530 312
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == *
chip_sw_rv_core_ibex_rnd 3837957873973252465467196053420184132619291294329283550221500562905241998022 319
UVM_INFO @ 184.673000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired
chip_sw_rv_core_ibex_nmi_irq 20905639196639777877875870459513507685810904122070521077504209224129817321353 322
UVM_INFO @ 272.201000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP
chip_sw_keymgr_dpe_key_derivation 23400128825208160554591176521192855198778509609389955670359408609199940700810 340
UVM_INFO @ 305.595000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_dpe_key_derivation_prod 51598244423477988127484622604308647491828445624953248232515499894918261424773 340
UVM_INFO @ 305.519000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 114610296574785385682963454655265945199936431906407132282444129797912595898614 231
TL item was: req: (cip_tl_seq_item@31637) { a_addr: 'h1465514 a_data: 'h85c6c43e a_mask: 'h2 a_size: 'h2 a_param: 'h0 a_source: 'hdd a_opcode: 'h1 a_user: 'h26a33 d_param: 'h0 d_source: 'hdd d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"} .
UVM_INFO @ 118.026000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_jtag_csr_rw 8440695975494210927072989312616628351936368428171133589966872048838527205006 5952
TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000 a_data: 'hf6848039 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h1 a_user: 'h2488f d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"} .
UVM_INFO @ 117.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_jtag_mem_access 94132539931233260758093074459475053022480368237164657313087873050747946637567 5952
TL item was: req: (cip_tl_seq_item@41718) { a_addr: 'h30480000 a_data: 'h489ff055 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h26979 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unmapped address"} .
UVM_INFO @ 117.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:695) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 55648735776759083662424469515788640620315586091406874869873026556807712301044 327
UVM_INFO @ 136.404500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure
chip_padctrl_attributes 18829874518140597433419805107978417004194128213753935253459172719155906717324 281
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 132
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *
chip_sw_dma_abort 96893470879501989889496949439151561165220636419242527692630078926075628642621 325
UVM_INFO @ 212.061000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---