Simulation Results: clkmgr

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.89 %
  • code
  • 68.94 %
  • assert
  • 89.05 %
  • func
  • 66.67 %
  • line
  • 82.06 %
  • branch
  • 87.42 %
  • cond
  • 76.35 %
  • toggle
  • 98.87 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 21.272us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.770s 18.664us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.370s 24.791us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.470s 61.637us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.820s 2.547us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
clkmgr_csr_aliasing 1.470s 61.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.750s 13.285us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.760s 14.862us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.820s 26.841us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 21.272us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.640s 5.230us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.560s 2.484us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.640s 5.230us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.710s 2.382us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.800s 16.683us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.440s 112.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.440s 112.699us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.770s 18.664us 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
clkmgr_csr_aliasing 1.470s 61.637us 1 1 100.00
clkmgr_same_csr_outstanding 1.200s 72.567us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.770s 18.664us 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
clkmgr_csr_aliasing 1.470s 61.637us 1 1 100.00
clkmgr_same_csr_outstanding 1.200s 72.567us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.490s 299.020us 1 1 100.00
clkmgr_tl_intg_err 0.770s 11.229us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 76.780us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 76.780us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 76.780us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 76.780us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.940s 23.945us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.770s 11.229us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.640s 5.230us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.560s 2.484us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.230s 76.780us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.960s 42.527us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.490s 299.020us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 16.300us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.490s 299.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.620s 3.133us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 2.290s 119.362us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 112888169779628970527333240791534018880899298548406863091945848860912545521017 75
UVM_INFO @ 5230118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 16882336347942371420775451143859692088204971618133634387113086542618218664084 77
UVM_INFO @ 2484262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 33136465820384244244027284660208988040414769611990013895285072719104474197247 149
UVM_INFO @ 119361879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 79765905099816144117416489438837103626906943524758455476528164063576430636773 77
UVM_INFO @ 2381992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 6812775184140546031443960789479005779629934357293807356850084855566753392340 74
UVM_INFO @ 3132715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 113697599608815190899578654557692326554572864726413503953936181444698886095112 75
UVM_INFO @ 23945388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 10546273990313892567880649156852823528994883495913131457190825139792243502241 85
UVM_INFO @ 11229443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 93079262753093387619936275659230090083931871971035279172094295480495896585696 75
UVM_INFO @ 24791408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 58358887831033234697584650586165205289460092944724233960008196149369896568087 75
UVM_INFO @ 72567467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_csr_mem_rw_with_rand_reset 75738015780192421193811216176094405635297381391861256867788530790411816880648 76
UVM_INFO @ 2547334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---