Simulation Results: edn/edn0

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.37 %
  • code
  • 81.84 %
  • assert
  • 96.31 %
  • func
  • 80.95 %
  • line
  • 97.93 %
  • branch
  • 92.89 %
  • cond
  • 87.64 %
  • toggle
  • 82.37 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 127.980us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 32.233us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 22.958us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.660s 352.441us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 15.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.910s 95.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 22.958us 1 1 100.00
edn_csr_aliasing 1.170s 15.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.590s 47.224us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.590s 47.224us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.590s 47.224us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.220s 25.509us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 75.602us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 33.447us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 11.682us 1 1 100.00
edn_disable_auto_req_mode 1.110s 54.340us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 619.495us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.030s 17.162us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.880s 35.147us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.240s 208.150us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.240s 208.150us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 32.233us 1 1 100.00
edn_csr_rw 0.860s 22.958us 1 1 100.00
edn_csr_aliasing 1.170s 15.770us 1 1 100.00
edn_same_csr_outstanding 1.020s 63.675us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 32.233us 1 1 100.00
edn_csr_rw 0.860s 22.958us 1 1 100.00
edn_csr_aliasing 1.170s 15.770us 1 1 100.00
edn_same_csr_outstanding 1.020s 63.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
edn_tl_intg_err 1.720s 193.493us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.080s 131.074us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 75.602us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 75.602us 1 1 100.00
edn_sec_cm 5.000s 1178.513us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 75.602us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.720s 193.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 57.590s 3497.052us 1 1 100.00