Simulation Results: edn/edn1

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.24 %
  • code
  • 84.96 %
  • assert
  • 97.14 %
  • func
  • 79.62 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 90.31 %
  • toggle
  • 95.70 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 30.316us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 86.152us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.900s 40.663us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.180s 1652.371us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.760s 165.900us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 135.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.900s 40.663us 1 1 100.00
edn_csr_aliasing 1.760s 165.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.330s 55.586us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.330s 55.586us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.330s 55.586us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.240s 20.023us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.250s 32.771us 1 1 100.00
errs 1 1 100.00
edn_err 1.190s 17.987us 1 1 100.00
disable 2 2 100.00
edn_disable 1.040s 124.452us 1 1 100.00
edn_disable_auto_req_mode 1.100s 73.973us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.450s 1146.945us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 27.077us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.030s 106.844us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.830s 250.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.830s 250.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.090s 86.152us 1 1 100.00
edn_csr_rw 0.900s 40.663us 1 1 100.00
edn_csr_aliasing 1.760s 165.900us 1 1 100.00
edn_same_csr_outstanding 1.070s 17.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.090s 86.152us 1 1 100.00
edn_csr_rw 0.900s 40.663us 1 1 100.00
edn_csr_aliasing 1.760s 165.900us 1 1 100.00
edn_same_csr_outstanding 1.070s 17.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
edn_tl_intg_err 2.540s 490.590us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 127.493us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.250s 32.771us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.250s 32.771us 1 1 100.00
edn_sec_cm 2.910s 426.878us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.250s 32.771us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.540s 490.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 18.530s 4088.311us 1 1 100.00