Simulation Results: hmac

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.35 %
  • code
  • 97.37 %
  • assert
  • 97.36 %
  • func
  • 43.32 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.160s 300.274us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.280s 43.724us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.040s 55.488us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 15.210s 3338.971us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.510s 789.043us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 49.390s 7566.502us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.040s 55.488us 1 1 100.00
hmac_csr_aliasing 2.510s 789.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 10.750s 693.075us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 46.500s 1421.525us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.190s 156.551us 1 1 100.00
hmac_test_sha384_vectors 402.210s 12302.221us 1 1 100.00
hmac_test_sha512_vectors 351.350s 9697.617us 1 1 100.00
hmac_test_hmac256_vectors 9.960s 319.294us 1 1 100.00
hmac_test_hmac384_vectors 8.170s 251.022us 1 1 100.00
hmac_test_hmac512_vectors 11.120s 1306.531us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.970s 1090.994us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 525.710s 14533.298us 1 1 100.00
error 1 1 100.00
hmac_error 32.280s 1418.137us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 102.590s 15937.972us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.160s 300.274us 1 1 100.00
hmac_long_msg 10.750s 693.075us 1 1 100.00
hmac_back_pressure 46.500s 1421.525us 1 1 100.00
hmac_datapath_stress 525.710s 14533.298us 1 1 100.00
hmac_burst_wr 13.970s 1090.994us 1 1 100.00
hmac_stress_all 46.500s 1245.554us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.160s 300.274us 1 1 100.00
hmac_long_msg 10.750s 693.075us 1 1 100.00
hmac_back_pressure 46.500s 1421.525us 1 1 100.00
hmac_datapath_stress 525.710s 14533.298us 1 1 100.00
hmac_wipe_secret 102.590s 15937.972us 1 1 100.00
hmac_test_sha256_vectors 10.190s 156.551us 1 1 100.00
hmac_test_sha384_vectors 402.210s 12302.221us 1 1 100.00
hmac_test_sha512_vectors 351.350s 9697.617us 1 1 100.00
hmac_test_hmac256_vectors 9.960s 319.294us 1 1 100.00
hmac_test_hmac384_vectors 8.170s 251.022us 1 1 100.00
hmac_test_hmac512_vectors 11.120s 1306.531us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.160s 300.274us 1 1 100.00
hmac_long_msg 10.750s 693.075us 1 1 100.00
hmac_back_pressure 46.500s 1421.525us 1 1 100.00
hmac_datapath_stress 525.710s 14533.298us 1 1 100.00
hmac_burst_wr 13.970s 1090.994us 1 1 100.00
hmac_error 32.280s 1418.137us 1 1 100.00
hmac_wipe_secret 102.590s 15937.972us 1 1 100.00
hmac_test_sha256_vectors 10.190s 156.551us 1 1 100.00
hmac_test_sha384_vectors 402.210s 12302.221us 1 1 100.00
hmac_test_sha512_vectors 351.350s 9697.617us 1 1 100.00
hmac_test_hmac256_vectors 9.960s 319.294us 1 1 100.00
hmac_test_hmac384_vectors 8.170s 251.022us 1 1 100.00
hmac_test_hmac512_vectors 11.120s 1306.531us 1 1 100.00
hmac_stress_all 46.500s 1245.554us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 46.500s 1245.554us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 18.112us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.830s 52.873us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.150s 139.056us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.150s 139.056us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.280s 43.724us 1 1 100.00
hmac_csr_rw 1.040s 55.488us 1 1 100.00
hmac_csr_aliasing 2.510s 789.043us 1 1 100.00
hmac_same_csr_outstanding 1.430s 66.500us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.280s 43.724us 1 1 100.00
hmac_csr_rw 1.040s 55.488us 1 1 100.00
hmac_csr_aliasing 2.510s 789.043us 1 1 100.00
hmac_same_csr_outstanding 1.430s 66.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.090s 414.575us 1 1 100.00
hmac_tl_intg_err 2.010s 85.631us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.010s 85.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.160s 300.274us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 0.890s 30.561us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 79.760s 23685.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.470s 348.428us 1 1 100.00