Simulation Results

Simulation Results: i2c

04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
84.61 %

code
81.43 %

assert
96.19 %

func
76.22 %

line
96.41 %

branch
92.33 %

cond
85.12 %

toggle
89.24 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	16.790s	1631.712us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.560s	2551.282us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.800s	22.557us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.680s	17.162us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.310s	337.278us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.120s	30.868us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.940s	61.970us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.680s	17.162us	1	1	100.00
	i2c_csr_aliasing	1.120s	30.868us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.860s	13.010us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	603.340s	161423.348us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	13.650s	3350.154us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.940s	51.481us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	61.680s	16881.979us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	33.260s	2058.523us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.970s	113.710us	1	1	100.00
	i2c_host_fifo_fmt_empty	12.440s	367.138us	1	1	100.00
	i2c_host_fifo_reset_rx	3.590s	870.408us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	70.170s	33952.547us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.840s	2627.132us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.730s	291.017us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.920s	519.412us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	112.330s	13900.953us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.970s	2455.181us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	22.610s	3147.945us	1	1	100.00
	i2c_target_intr_smoke	5.220s	1578.001us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.410s	255.636us	1	1	100.00
	i2c_target_fifo_reset_tx	0.990s	260.199us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	73.590s	43860.292us	1	1	100.00
	i2c_target_stress_rd	22.610s	3147.945us	1	1	100.00
	i2c_target_intr_stress_wr	8.470s	1853.244us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.260s	1169.183us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	4.210s	5758.267us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.460s	1892.021us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.730s	440.698us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.200s	377.004us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.970s	76.222us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	13.650s	3350.154us	1	1	100.00
	i2c_host_perf_precise	2.190s	354.315us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.840s	2627.132us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.170s	163.737us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.140s	1233.175us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.980s	518.189us	1	1	100.00
	i2c_target_nack_txstretch	1.360s	194.832us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.080s	973.975us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.670s	6218.724us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.680s	181.127us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.810s	17.662us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.010s	210.342us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.010s	210.342us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	22.557us	1	1	100.00
	i2c_csr_rw	0.680s	17.162us	1	1	100.00
	i2c_csr_aliasing	1.120s	30.868us	1	1	100.00
	i2c_same_csr_outstanding	0.850s	107.055us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	22.557us	1	1	100.00
	i2c_csr_rw	0.680s	17.162us	1	1	100.00
	i2c_csr_aliasing	1.120s	30.868us	1	1	100.00
	i2c_same_csr_outstanding	0.850s	107.055us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.970s	459.286us	1	1	100.00
	i2c_sec_cm	0.800s	47.287us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.970s	459.286us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	7.590s	1498.566us	1
target_error_intr				1
	i2c_target_unexp_stop	0.980s	181.639us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	17.170s	599.323us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	115462575474747119252649847035050297313292389319736023697821661344765795467807	80	UVM_INFO @ 13010259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	79439114103981078067605447565091250085086738143241613333848316368248452900266	140	UVM_INFO @ 161423347555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	99461978359830734552346476700086168190759991911802909551891869150897483158611	84	UVM_INFO @ 519412247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	59810443457628917219316814516053477172319234921777601364819531898866159722923	78	UVM_INFO @ 181638837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	93221220054048387106710860658053429881945484448040404035945290541716222682630	88	UVM_INFO @ 1498565814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	25654666131135047420565446293742850790429159834804101942982078484240239639991	122	UVM_INFO @ 599323139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	16700656640956052470463043873762464491417769063683821212016307584876402392096	79	UVM_INFO @ 291016622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---