Simulation Results: kmac/unmasked

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 88.82 %
  • assert
  • 97.75 %
  • func
  • 92.35 %
  • line
  • 97.27 %
  • branch
  • 95.20 %
  • cond
  • 93.79 %
  • toggle
  • 100.00 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 19.770s 6411.537us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.190s 70.577us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.270s 39.427us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 13.800s 967.511us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.820s 199.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.600s 28.130us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.270s 39.427us 1 1 100.00
kmac_csr_aliasing 3.820s 199.119us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.990s 14.018us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.760s 45.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 473.040s 7314.274us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 522.010s 23631.403us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 32.310s 7392.292us 1 1 100.00
kmac_test_vectors_sha3_256 21.760s 1155.645us 1 1 100.00
kmac_test_vectors_sha3_384 20.780s 7029.014us 1 1 100.00
kmac_test_vectors_sha3_512 13.830s 1339.599us 1 1 100.00
kmac_test_vectors_shake_128 159.490s 57463.980us 1 1 100.00
kmac_test_vectors_shake_256 1735.730s 349780.087us 1 1 100.00
kmac_test_vectors_kmac 2.200s 114.392us 1 1 100.00
kmac_test_vectors_kmac_xof 3.050s 1493.657us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 189.020s 11420.723us 1 1 100.00
app 1 1 100.00
kmac_app 203.440s 45700.553us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 34.950s 3012.740us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 228.020s 23581.910us 1 1 100.00
error 1 1 100.00
kmac_error 120.570s 2399.812us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.490s 994.319us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 42.900s 10046.112us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 20.160s 378.691us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 22.720s 1191.358us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 42.300s 25944.438us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.620s 79.925us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 931.420s 209158.692us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.800s 28.170us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.810s 26.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.800s 38.895us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.800s 38.895us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.190s 70.577us 1 1 100.00
kmac_csr_rw 1.270s 39.427us 1 1 100.00
kmac_csr_aliasing 3.820s 199.119us 1 1 100.00
kmac_same_csr_outstanding 2.290s 124.921us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.190s 70.577us 1 1 100.00
kmac_csr_rw 1.270s 39.427us 1 1 100.00
kmac_csr_aliasing 3.820s 199.119us 1 1 100.00
kmac_same_csr_outstanding 2.290s 124.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 53.938us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.450s 53.938us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 53.938us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.450s 53.938us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.860s 60.331us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 28.230s 11663.299us 1 1 100.00
kmac_tl_intg_err 4.720s 110.375us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.720s 110.375us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.620s 79.925us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 19.770s 6411.537us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 189.020s 11420.723us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.450s 53.938us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 28.230s 11663.299us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 28.230s 11663.299us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 28.230s 11663.299us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 19.770s 6411.537us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.620s 79.925us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 28.230s 11663.299us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 55.110s 2523.312us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 19.770s 6411.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 75.150s 4047.180us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 30351829284204482956592149751281927965529886654586979285137420512753661027902 79
UVM_INFO @ 10046111989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---