Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.99 %
  • code
  • 84.34 %
  • assert
  • 95.99 %
  • func
  • 92.63 %
  • line
  • 97.69 %
  • branch
  • 96.56 %
  • cond
  • 79.02 %
  • toggle
  • 88.42 %
  • FSM
  • 60.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.360s 183.654us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 32.023us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.060s 72.106us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.740s 218.658us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 29.792us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 26.690us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.060s 72.106us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 29.792us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.630s 360.343us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.090s 3293.376us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.290s 13.014us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.250s 108.613us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.750s 7035.051us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_prog_failure 2.250s 108.613us 1 1 100.00
lc_ctrl_errors 5.750s 7035.051us 1 1 100.00
lc_ctrl_security_escalation 5.470s 2938.621us 1 1 100.00
lc_ctrl_jtag_state_failure 33.390s 4860.039us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.860s 1048.721us 1 1 100.00
lc_ctrl_jtag_errors 28.050s 1506.344us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.790s 3848.585us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.020s 752.638us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.860s 1048.721us 1 1 100.00
lc_ctrl_jtag_errors 28.050s 1506.344us 1 1 100.00
lc_ctrl_jtag_access 3.440s 1804.193us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.670s 5283.934us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.860s 57.664us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.040s 35.914us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.810s 540.658us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.670s 3673.133us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.290s 65.479us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.380s 89.412us 1 1 100.00
lc_ctrl_jtag_alert_test 0.890s 26.954us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.110s 345.614us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.100s 22.467us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 105.290s 12186.404us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.400s 88.190us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 69.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.660s 69.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 32.023us 1 1 100.00
lc_ctrl_csr_rw 1.060s 72.106us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 29.792us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 25.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 32.023us 1 1 100.00
lc_ctrl_csr_rw 1.060s 72.106us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 29.792us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 25.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
lc_ctrl_tl_intg_err 1.290s 92.894us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.290s 92.894us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.090s 3293.376us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.510s 297.855us 1 1 100.00
lc_ctrl_sec_cm 5.440s 541.404us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.470s 2938.621us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.630s 360.343us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.020s 752.638us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.500s 768.770us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.500s 768.770us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.450s 1829.052us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.170s 3616.601us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.170s 3616.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 70.240s 2812.502us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 72069173684242961724707490771594632994175060192920140595435078677705321536299 3116
UVM_INFO @ 2812501936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---