Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.24 %
  • code
  • 86.80 %
  • assert
  • 95.85 %
  • func
  • 94.06 %
  • line
  • 97.82 %
  • branch
  • 96.22 %
  • cond
  • 80.03 %
  • toggle
  • 89.02 %
  • FSM
  • 70.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.410s 1167.076us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.980s 28.822us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 109.326us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.290s 26.380us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 56.177us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.460s 24.063us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 109.326us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 56.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.950s 172.087us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.860s 650.726us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 15.061us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.520s 32.267us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.030s 557.050us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_prog_failure 1.520s 32.267us 1 1 100.00
lc_ctrl_errors 5.030s 557.050us 1 1 100.00
lc_ctrl_security_escalation 9.280s 3027.815us 1 1 100.00
lc_ctrl_jtag_state_failure 19.690s 8584.695us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.870s 2232.551us 1 1 100.00
lc_ctrl_jtag_errors 41.110s 42146.532us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.470s 168.772us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.920s 820.625us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.870s 2232.551us 1 1 100.00
lc_ctrl_jtag_errors 41.110s 42146.532us 1 1 100.00
lc_ctrl_jtag_access 4.350s 4674.819us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.670s 1193.813us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.580s 362.881us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.680s 347.934us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.590s 757.098us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.570s 5780.375us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.940s 25.897us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.900s 79.835us 1 1 100.00
lc_ctrl_jtag_alert_test 1.150s 431.124us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.840s 860.915us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.880s 77.455us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 178.250s 150995.379us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 149.130us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.700s 252.475us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.700s 252.475us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 28.822us 1 1 100.00
lc_ctrl_csr_rw 0.730s 109.326us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 56.177us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 163.023us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 28.822us 1 1 100.00
lc_ctrl_csr_rw 0.730s 109.326us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 56.177us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 163.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 122.372us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 122.372us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.860s 650.726us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.890s 2487.983us 1 1 100.00
lc_ctrl_sec_cm 5.240s 1228.144us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.280s 3027.815us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.950s 172.087us 1 1 100.00
lc_ctrl_jtag_state_post_trans 17.920s 820.625us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.350s 421.061us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.350s 421.061us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.100s 479.969us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.880s 781.810us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.880s 781.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.620s 109.165us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 68615207337373811922349021980864514595677719776324625770122600371709802406804 199
UVM_INFO @ 109164916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---