Simulation Results: otbn

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.34 %
  • code
  • 95.35 %
  • assert
  • 89.78 %
  • func
  • 97.88 %
  • block
  • 99.39 %
  • line
  • 99.57 %
  • branch
  • 92.21 %
  • toggle
  • 92.17 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 45.245us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 47.557us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 45.375us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 291.614us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 28.845us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 88.585us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 45.375us 1 1 100.00
otbn_csr_aliasing 3.000s 28.845us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 42.000s 11430.187us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 35.000s 1045.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 117.423us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 132.844us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 60.000s 347.945us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 53.000s 269.918us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 72.227us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 19.775us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 22.579us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 21.738us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 39.085us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 38.155us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 38.155us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 47.557us 1 1 100.00
otbn_csr_rw 4.000s 45.375us 1 1 100.00
otbn_csr_aliasing 3.000s 28.845us 1 1 100.00
otbn_same_csr_outstanding 4.000s 85.354us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 47.557us 1 1 100.00
otbn_csr_rw 4.000s 45.375us 1 1 100.00
otbn_csr_aliasing 3.000s 28.845us 1 1 100.00
otbn_same_csr_outstanding 4.000s 85.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 61.652us 1 1 100.00
otbn_dmem_err 7.000s 49.238us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 14.000s 30.121us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 56.140us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 109.245us 1 1 100.00
otbn_urnd_err 3.000s 22.155us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 31.011us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 14.723us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 14.935us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
otbn_tl_intg_err 9.000s 120.825us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 50.000s 244.854us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 45.245us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 49.238us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 61.652us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 120.825us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 72.227us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 61.652us 1 1 100.00
otbn_dmem_err 7.000s 49.238us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 19.775us 0 1 0.00
otbn_illegal_mem_acc 8.000s 31.011us 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 61.652us 1 1 100.00
otbn_dmem_err 7.000s 49.238us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 19.775us 0 1 0.00
otbn_illegal_mem_acc 8.000s 31.011us 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 72.227us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 61.652us 1 1 100.00
otbn_dmem_err 7.000s 49.238us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 19.775us 0 1 0.00
otbn_illegal_mem_acc 8.000s 31.011us 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 31.909us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 40.911us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 67.000s 191.646us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 67.000s 191.646us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 43.375us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 224.026us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 20.385us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 20.385us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 11.000s 170.964us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 60.000s 347.945us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 5.000s 20.259us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 10.731us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 88.000s 2051.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 131.000s 778.415us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 35.556us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 39638965224294762122555592027039447559808677419176165818507314068409418979817 182
UVM_INFO @ 778415485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 33073412671024676929925351514817383940483737030123717003848401197924140801381 109
UVM_INFO @ 19774690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 54890935431243289631363775670297997809428586470561068492759601414403230820284 103
UVM_INFO @ 22154636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---