Simulation Results: rom_ctrl/32kb

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 96.78 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 100.00 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.330s 314.876us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.440s 184.514us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.990s 387.397us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.580s 173.256us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 209.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.610s 181.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.990s 387.397us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 209.478us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.700s 169.919us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.930s 126.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.670s 142.709us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.330s 475.297us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 1088.762us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.940s 291.854us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.690s 130.766us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.690s 130.766us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.440s 184.514us 1 1 100.00
rom_ctrl_csr_rw 2.990s 387.397us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 209.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.650s 704.620us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.440s 184.514us 1 1 100.00
rom_ctrl_csr_rw 2.990s 387.397us 1 1 100.00
rom_ctrl_csr_aliasing 3.710s 209.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.650s 704.620us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.020s 5852.807us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
rom_ctrl_tl_intg_err 42.060s 1609.765us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.330s 314.876us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.330s 314.876us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.330s 314.876us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.060s 1609.765us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 1088.762us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.910s 2063.512us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.020s 5852.807us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.960s 1205.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 291.670s 3780.421us 1 1 100.00