Simulation Results: rom_ctrl/64kb

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.81 %
  • code
  • 99.25 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 99.97 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.340s 256.035us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.640s 1222.122us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.430s 1026.118us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.190s 1538.391us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.650s 727.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.070s 565.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.430s 1026.118us 1 1 100.00
rom_ctrl_csr_aliasing 5.650s 727.243us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.540s 1027.556us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.190s 385.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.080s 414.373us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.900s 598.570us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 2103.628us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.630s 726.136us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.620s 319.898us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.620s 319.898us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.640s 1222.122us 1 1 100.00
rom_ctrl_csr_rw 7.430s 1026.118us 1 1 100.00
rom_ctrl_csr_aliasing 5.650s 727.243us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.670s 729.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.640s 1222.122us 1 1 100.00
rom_ctrl_csr_rw 7.430s 1026.118us 1 1 100.00
rom_ctrl_csr_aliasing 5.650s 727.243us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.670s 729.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.660s 8632.816us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
rom_ctrl_tl_intg_err 54.670s 473.922us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.340s 256.035us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.340s 256.035us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.340s 256.035us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 54.670s 473.922us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
rom_ctrl_kmac_err_chk 13.800s 2103.628us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 130.320s 11872.098us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.660s 8632.816us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 246.280s 1576.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 135.250s 2891.162us 1 1 100.00