Simulation Results: rstmgr

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.21 %
  • code
  • 99.43 %
  • assert
  • 97.62 %
  • func
  • 94.58 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.09 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.150s 69.865us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.080s 65.197us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.220s 67.237us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.490s 54.468us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.080s 64.562us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00
rstmgr_csr_aliasing 1.490s 54.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.530s 159.703us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.040s 37.510us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.790s 38.007us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.500s 558.393us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.500s 558.393us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.500s 558.393us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.500s 558.393us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.570s 2561.857us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.000s 44.879us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.860s 62.213us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.860s 62.213us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 65.197us 1 1 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00
rstmgr_csr_aliasing 1.490s 54.468us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 38.838us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.080s 65.197us 1 1 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00
rstmgr_csr_aliasing 1.490s 54.468us 1 1 100.00
rstmgr_same_csr_outstanding 0.980s 38.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 33.900s 6740.962us 1 1 100.00
rstmgr_tl_intg_err 4.230s 623.328us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 33.900s 6740.962us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 33.900s 6740.962us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.230s 623.328us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.980s 63.115us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.760s 463.035us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.010s 290.815us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 33.900s 6740.962us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 37.413us 1 1 100.00