Simulation Results: rv_dm/use_dmi_interface

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.83 %
  • code
  • 72.76 %
  • assert
  • 96.16 %
  • func
  • 49.57 %
  • line
  • 89.85 %
  • branch
  • 74.15 %
  • cond
  • 75.91 %
  • toggle
  • 70.75 %
  • FSM
  • 53.12 %
Validation stages
V1
96.30%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 2.530s 773.492us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.780s 832.239us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.550s 818.367us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 8.350s 3772.707us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 2.810s 2137.882us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 37.870s 19665.859us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 2.190s 5142.109us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 6.290s 4682.593us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 158.180s 220942.748us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.110s 382.426us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.370s 1003.553us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 1.140s 165.084us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 0.940s 388.601us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.000s 93.379us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.610s 2597.045us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.910s 134.536us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.580s 724.895us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.110s 382.426us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.580s 368.934us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.310s 584.362us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 1.140s 165.084us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.850s 134.564us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.800s 183.423us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.450s 162.129us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 64.390s 38333.213us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 17.980s 1191.892us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.960s 101.438us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 17.980s 1191.892us 1 1 100.00
rv_dm_csr_rw 1.450s 162.129us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.930s 104.637us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.860s 166.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 2.530s 773.492us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.170s 813.489us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.880s 280.090us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.910s 526.014us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 6.930s 2538.929us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 3.120s 1381.246us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 1.070s 455.711us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 12.090s 7768.936us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 11.550s 6390.526us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.640s 128.220us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 2.280s 1291.116us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 0.870s 106.687us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 1.100s 393.355us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 5.090s 6598.491us 1 1 100.00
rv_dm_tap_fsm_rand_reset 31.380s 3120.894us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.880s 130.286us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.960s 175.459us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.790s 125.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 4.100s 504.575us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 4.100s 504.575us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 17.980s 1191.892us 1 1 100.00
rv_dm_csr_hw_reset 1.800s 183.423us 1 1 100.00
rv_dm_csr_rw 1.450s 162.129us 1 1 100.00
rv_dm_same_csr_outstanding 2.690s 100.414us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 17.980s 1191.892us 1 1 100.00
rv_dm_csr_hw_reset 1.800s 183.423us 1 1 100.00
rv_dm_csr_rw 1.450s 162.129us 1 1 100.00
rv_dm_same_csr_outstanding 2.690s 100.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 1.480s 294.562us 1 1 100.00
rv_dm_tl_intg_err 7.640s 2548.614us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 7.640s 2548.614us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 2.280s 1291.116us 1 1 100.00
rv_dm_debug_disabled 1.030s 68.543us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 2.280s 1291.116us 1 1 100.00
rv_dm_debug_disabled 1.030s 68.543us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 2.530s 773.492us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 2.570s 684.002us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.840s 54.030us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.840s 54.030us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 2.570s 684.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 5.910s 1035.083us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 274.250s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:
rv_dm_sba_tl_access 83344607644674867551920972177746917023742101009946193226064911866564764479003 86
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5652
rv_dm_bad_sba_tl_access 62729883462892485924749918149303318407403037121667022044039316625225699294952 116
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @13438
rv_dm_autoincr_sba_tl_access 107809969656810360226179134423989339524996400191168541212600505736849090368258 122
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @11262
Error-[CNST-CIF] Constraints inconsistency failure
rv_dm_delayed_resp_sba_tl_access 15608654113434911668878248937921800980552171332738058563921947775009804915850 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 50634386826641260231769574912506328190178773961995957284811877624042845192306 77
UVM_INFO @ 388600670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 98706071878161453805317314040389787573689916128468013322887248170233312859153 78
UVM_INFO @ 175458535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 63850425145952815978302080067304245024657897510225730362803938007398808525888 77
UVM_INFO @ 393354976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 74424109710493891932389267618217032275881110114091813772353229565913311902547 84
UVM_INFO @ 1035083101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 81871206147948660170660364127212865400343482878959645390303372197560870587722 77
UVM_INFO @ 128220176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
rv_dm_debug_disabled 15017159946152300213158890475657319620598963578131647513334684189106167012542 80
UVM_INFO @ 68542613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_scanmode 664347713122975783759730896497180917914625805392988211318724453380216389023 77
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---