Simulation Results: rv_timer

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.130s 929.103us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 109.239us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 19.795us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.430s 462.433us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.940s 64.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 20.484us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 19.795us 1 1 100.00
rv_timer_csr_aliasing 0.940s 64.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.590s 24.860us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.500s 1614.352us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 124.250s 318972.784us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 124.250s 318972.784us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.330s 1338.595us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.600s 13.963us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 158.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.170s 52.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.170s 52.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 109.239us 1 1 100.00
rv_timer_csr_rw 0.560s 19.795us 1 1 100.00
rv_timer_csr_aliasing 0.940s 64.260us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 77.773us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 109.239us 1 1 100.00
rv_timer_csr_rw 0.560s 19.795us 1 1 100.00
rv_timer_csr_aliasing 0.940s 64.260us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 77.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.950s 659.548us 1 1 100.00
rv_timer_tl_intg_err 1.420s 127.014us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.420s 127.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.680s 71.415us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.760s 45.963us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 24.230s 5841.071us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 38597010579873023931092503438837964565901831254816269049103500896283381317891 75
UVM_INFO @ 71414939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 105562604380265634984373162404653609650705099561235804128407601462790118255441 75
UVM_INFO @ 45963267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---