Simulation Results: spi_device/1r1w

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.89 %
  • code
  • 93.31 %
  • assert
  • 94.39 %
  • func
  • 72.97 %
  • line
  • 99.05 %
  • branch
  • 98.25 %
  • cond
  • 96.34 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 34.470s 12491.638us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.180s 44.114us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.160s 41.909us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.830s 1219.579us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.760s 1281.191us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.770s 51.738us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.160s 41.909us 1 1 100.00
spi_device_csr_aliasing 5.760s 1281.191us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.770s 19.677us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.290s 32.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.770s 61.263us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.860s 2.166us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.660s 3.176us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.700s 11.830us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.700s 11.830us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.730s 10.544us 1 1 100.00
spi_device_tpm_sts_read 0.850s 68.760us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 7.080s 565.863us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.820s 16179.264us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.400s 7757.932us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 14.400s 7757.932us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.020s 527.407us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.020s 527.407us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.020s 527.407us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.020s 527.407us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.020s 527.407us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.250s 8848.948us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.660s 259.634us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.660s 259.634us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.660s 259.634us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 13.270s 6266.500us 1 1 100.00
spi_device_read_buffer_direct 2.820s 293.124us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.660s 259.634us 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 23.330s 2790.723us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 10.630s 1292.398us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 10.630s 1292.398us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 34.470s 12491.638us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 153.490s 48194.301us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 21.000s 5873.162us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.850s 47.117us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.820s 45.508us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.260s 707.636us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.260s 707.636us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 44.114us 1 1 100.00
spi_device_csr_rw 1.160s 41.909us 1 1 100.00
spi_device_csr_aliasing 5.760s 1281.191us 1 1 100.00
spi_device_same_csr_outstanding 1.640s 86.217us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.180s 44.114us 1 1 100.00
spi_device_csr_rw 1.160s 41.909us 1 1 100.00
spi_device_csr_aliasing 5.760s 1281.191us 1 1 100.00
spi_device_same_csr_outstanding 1.640s 86.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.040s 164.695us 1 1 100.00
spi_device_tl_intg_err 9.150s 414.939us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.150s 414.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 328.220s 84176.885us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 87844736356088617129489670710186798484851448285258510396991799324717564148873 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1819965 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1819965 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 30891366124356332370723873753943300917928397108112023471192606278083794474055 76
UVM_ERROR @ 819516 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd97b45 [110110010111101101000101] vs 0x0 [0])
UVM_ERROR @ 904516 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9b8f48 [100110111000111101001000] vs 0x0 [0])
UVM_ERROR @ 1004516 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe02166 [111000000010000101100110] vs 0x0 [0])
UVM_ERROR @ 1068516 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3cb41 [111100101101000001] vs 0x0 [0])