Simulation Results: sram_ctrl/main

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.12 %
  • code
  • 96.83 %
  • assert
  • 96.32 %
  • func
  • 92.20 %
  • block
  • 96.15 %
  • line
  • 96.88 %
  • branch
  • 94.33 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1721.700us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 59.711us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.718us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 103.442us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 128.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1709.914us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 17.718us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 128.646us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 101.000s 7225.498us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.000s 5900.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 36.000s 40209.838us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 3922.751us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 159.000s 42779.078us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 34.000s 26271.823us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 16.000s 18644.240us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 32.000s 7344.515us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2797.461us 1 1 100.00
sram_ctrl_partial_access_b2b 114.000s 25002.687us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 722.912us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 4748.791us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2772.039us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 21.000s 25898.050us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1461.909us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 239.000s 70752.085us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.461us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 169.446us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 169.446us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 59.711us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.718us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 128.646us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.057us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 59.711us 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.718us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 128.646us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 14382.403us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 100.059us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 100.059us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 21.000s 25898.050us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 21.000s 25898.050us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 17.718us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 32.000s 7344.515us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 7344.515us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 7344.515us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 16.000s 18644.240us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 688.576us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 14382.403us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 2567.363us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1721.700us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1721.700us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 32.000s 7344.515us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 16.000s 18644.240us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1721.700us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2495.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 1131.231us 1 1 100.00