Simulation Results: sram_ctrl/ret

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.47 %
  • code
  • 83.11 %
  • assert
  • 96.29 %
  • func
  • 95.00 %
  • block
  • 93.46 %
  • line
  • 94.59 %
  • branch
  • 88.89 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 565.571us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.970us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.156us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 96.499us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.217us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 46.281us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 33.156us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.217us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 2614.970us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 142.757us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 1319.243us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 149.000s 40127.859us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 874.672us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 2161.126us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1207.819us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 1343.915us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 365.646us 1 1 100.00
sram_ctrl_partial_access_b2b 167.000s 46462.473us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 35.133us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 107.184us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 244.541us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 552.981us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 111.734us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 37.000s 1861.288us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 61.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 30.565us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 30.565us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.970us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.156us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.217us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.809us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.970us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.156us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.217us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 809.525us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 210.307us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 210.307us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 552.981us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 552.981us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.156us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1343.915us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1343.915us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 1343.915us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1207.819us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 64.400us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 809.525us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 50.237us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 565.571us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 565.571us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 1343.915us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 1207.819us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 565.571us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 404.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 170.947us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 24151616357150752192602993035411807454669339190760355978714952403731177171609 88
UVM_INFO @ 46281489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---